公开(公告)号：US20190042199A1

公开(公告)日：2019-02-07

申请号：US16147004

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Huseyin Ekin SUMBUL ,  Phil KNAG ,  Gregory K. CHEN ,  Raghavan KUMAR ,  Abhishek SHARMA ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Ram KRISHNAMURTHY ,  Ian A. YOUNG

IPC: G06F7/544 ,  G11C8/10 ,  G11C7/12 ,  G11C8/08 ,  G06N3/08

Abstract: Compute-in memory circuits and techniques are described. In one example, a memory device includes an array of memory cells, the array including multiple sub-arrays. Each of the sub-arrays receives a different voltage. The memory device also includes capacitors coupled with conductive access lines of each of the multiple sub-arrays and circuitry coupled with the capacitors, to share charge between the capacitors in response to a signal. In one example, computing device, such as a machine learning accelerator, includes a first memory array and a second memory array. The computing device also includes an analog processor circuit coupled with the first and second memory arrays to receive first analog input voltages from the first memory array and second analog input voltages from the second memory array and perform one or more operations on the first and second analog input voltages, and output an analog output voltage.

公开(公告)号：US20190019793A1

公开(公告)日：2019-01-17

申请号：US16080914

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Daniel H, MORRIS ,  Uygar E. AVCI ,  Ian A. YOUNG

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L21/823437 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78

Abstract: One embodiment provides an apparatus. The apparatus includes a first transistor and a second transistor. The first transistor includes a first drain, a first source coupled to the first drain by a first channel, and a first gate stack comprising a plurality of layers. The second transistor includes a second drain, a second source coupled to the second drain by a second channel, and a second gate stack comprising a plurality of layers. Each gate stack includes a work function material layer to optimize a threshold voltage variation between the transistors.

公开(公告)号：US20170345496A1

公开(公告)日：2017-11-30

申请号：US15164665

申请日：2016-05-25

Applicant: Intel Corporation

Inventor： Huichu LIU ,  Daniel H. MORRIS ,  Sasikanth MANIPATRUNI ,  Kaushik VAIDYANATHAN ,  Ian A. YOUNG ,  Tanay KARNIK

IPC: G11C13/00 ,  G11C11/16

CPC classification number: G11C13/0069 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0097 ,  G11C2013/0042 ,  G11C2213/79 ,  G11C2213/82

Abstract: An apparatus is provided which comprises: a select line; a select transistor coupled to a resistive memory element and to the select line; a word-line coupled to a gate terminal of the select transistor; and a current mirror operable to be coupled to the select line during a first mode and to be de-coupled during a second mode.

公开(公告)号：US20170271501A1

公开(公告)日：2017-09-21

申请号：US15505558

申请日：2014-09-24

Applicant: Intel Corporation

Inventor： Uygar E. AVCI ,  Rafael RIOS ,  Kelin J. KUHN ,  Ian A. YOUNG ,  Justin R. WEBER

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/16 ,  H01L29/24 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/785 ,  B82Y10/00 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/66795 ,  H01L29/7391

Abstract: Described is a TFET comprising: a nanowire having doped regions for forming source and drain regions, and an un-doped region for coupling to a gate region; and a first termination material formed over the nanowire; and a second termination material formed over a section of the nanowire overlapping the gate and source regions. Described is another TFET comprising: a first section of a nanowire having doped regions for forming source and drain regions, and an undoped region for coupling to a gate region; a second section of the nanowire extending orthogonal to the first section, the second section formed next to the gate and source regions; and a termination material formed over the first and second sections of the nanowire.

公开(公告)号：US20160276440A1

公开(公告)日：2016-09-22

申请号：US15037296

申请日：2013-12-23

Applicant: INTEL CORPORATION

Inventor： Uygar E. Avci ,  Roza KOTLYAR ,  Gilbert DEWEY ,  Benjamin CHU-KUNG ,  Ian A. YOUNG

IPC: H01L29/12 ,  H01L29/205 ,  H01L29/165 ,  G11C5/06 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/125 ,  G11C5/06 ,  H01L29/0669 ,  H01L29/165 ,  H01L29/205 ,  H01L29/7391 ,  H01L29/7831

Abstract: Embodiments of the disclosure described herein comprise a tunneling field effect transistor (TFET) having a drain region, a source region having a conductivity type opposite of the drain region, a channel region disposed between the source region and the drain region, a gate disposed over the channel region, and a heterogeneous pocket disposed near a junction of the source region and the channel region. The heterogeneous pocket comprises a semiconductor material different than the channel region, and comprises a tunneling barrier less than the bandgap in the channel region and forming a quantum well in the channel region to in crease a current through the TFET transistor when a voltage applied to the gate is above a threshold voltage.

Abstract translation: 本文所述的本发明的实施例包括具有漏极区域，具有与漏极区域相反的导电类型的源极区域的沟道场效应晶体管（TFET），设置在源极区域和漏极区域之间的沟道区域，栅极设置在 沟道区域和设置在源区域和沟道区域的结点附近的异质袋。 异质袋包括不同于沟道区的半导体材料，并且包括小于沟道区中的带隙的隧穿势垒，并且在施加到栅极的电压时在通道区中形成量子阱以增加通过TFET晶体管的电流 门高于阈值电压。

公开(公告)号：US20230102177A1

公开(公告)日：2023-03-30

申请号：US17484981

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Chia-Ching LIN ,  Sou-Chi CHANG ,  Kaan OGUZ ,  I-Cheng TUNG ,  Arnab SEN GUPTA ,  Ian A. YOUNG ,  Uygar E. AVCI ,  Matthew V. METZ

IPC: H01G4/08 ,  H01L49/02 ,  H01G4/30

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to stacked MIM capacitors with multiple metal and dielectric layers that include insulating spacers on edges of one or more of the multiple layers to prevent unintended electrical coupling between metal layers during manufacturing. The dielectric layers may include Perovskite-based materials. Other embodiments may be described and/or claimed.

公开(公告)号：US20230101604A1

公开(公告)日：2023-03-30

申请号：US17485314

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Ashish Verma PENUMATCHA ,  Uygar E. AVCI ,  Tanay GOSAVI ,  Shriram SHIVARAMAN ,  Carl H. NAYLOR ,  Chelsey DOROW ,  Ian A. YOUNG ,  Nazila HARATIPOUR ,  Kevin P. O'BRIEN

IPC: H01L29/76 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11597 ,  H01L29/24

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to three-dimensional (3D) memory devices with transition metal dichalcogenide (TMD) channels. Other embodiments may be disclosed or claimed.

公开(公告)号：US20230057992A1

公开(公告)日：2023-02-23

申请号：US17406296

申请日：2021-08-19

Applicant: Intel Corporation

Inventor： Tanay GOSAVI ,  Raseong KIM ,  Han Wui THEN ,  Ian A. YOUNG

IPC: H01L27/20 ,  H01L29/20 ,  H01L29/778 ,  H03H9/02 ,  H03H9/17 ,  H01L29/66 ,  H03H3/02

Abstract: Gallium nitride (GaN) integrated circuit technology with resonators is described. In an example, an integrated circuit structure includes a layer or substrate including gallium and nitrogen. A first plurality of electrodes is over the layer or substrate. A resonator layer is on the first plurality of electrodes, the resonator layer including aluminum and nitrogen. A second plurality of electrodes is on the resonator layer. Individual ones of the second plurality of electrodes are vertically over and aligned with corresponding individual ones of the first plurality of electrodes.

公开(公告)号：US20220012581A1

公开(公告)日：2022-01-13

申请号：US17484828

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Abhishek SHARMA ,  Jack T. KAVALIEROS ,  Ian A. YOUNG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Uygar AVCI ,  Gregory K. CHEN ,  Amrita MATHURIYA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin Ekin SUMBUL ,  Nazila HARATIPOUR ,  Van H. LE

IPC: G06N3/063 ,  H01L27/108 ,  H01L27/11502 ,  G06N3/04 ,  G06F17/16 ,  H01L27/11 ,  G11C11/54 ,  G11C7/10

Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

公开(公告)号：US20200312949A1

公开(公告)日：2020-10-01

申请号：US16368450

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Nazila HARATIPOUR ,  Chia-Ching LIN ,  Sou-Chi CHANG ,  Ashish Verma PENUMATCHA ,  Owen LOH ,  Mengcheng LU ,  Seung Hoon SUNG ,  Ian A. YOUNG ,  Uygar AVCI ,  Jack T. KAVALIEROS

IPC: H01L49/02 ,  H01G4/30 ,  H01G4/012 ,  H01L27/11585 ,  H01L23/522

Abstract: A capacitor is disclosed. The capacitor includes a first metal layer, a second metal layer on the first metal layer, a ferroelectric layer on the second metal layer, and a third metal layer on the ferroelectric layer. The second metal layer includes a first non-reactive barrier metal and the third metal layer includes a second non-reactive barrier metal. A fourth metal layer is on the third metal layer.