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公开(公告)号：US10949736B2
公开(公告)日：2021-03-16
申请号：US15343036
申请日：2016-11-03
Applicant: INTEL CORPORATION
Inventor： Michael E Deisher , Ohad Falik
Abstract: Systems, apparatus and methods are described including operations for a flexible neural network accelerator.
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公开(公告)号：US20180060246A1
公开(公告)日：2018-03-01
申请号：US15803244
申请日：2017-11-03
Applicant: Intel Corporation
Inventor： Ben-Zion Friedman , Jacob Doweck , Eliezer Weissmann , James B. Crossland , Ohad Falik
IPC: G06F12/10
CPC classification number: G06F12/1009 , G06F12/10 , G06F12/1027 , G06F12/1036 , G06F2212/1016 , G06F2212/507 , G06F2212/65 , G06F2212/657 , G06F2212/68
Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.
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公开(公告)号：US09904346B2
公开(公告)日：2018-02-27
申请号：US14716326
申请日：2015-05-19
Applicant: Intel Corporation
Inventor： Ryan D. Wells , Ohad Falik , Jose P. Allarey
CPC classification number: G06F1/324 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/3234 , G06F1/3237 , G06F1/3243 , G06F1/3246 , G06F1/3287 , G06F1/329 , G06F1/3293 , G06F1/3296 , G06F9/5027 , G06F9/5094 , G06F2209/501 , Y02D10/126 , Y02D10/17 , Y02D10/171 , Y02D10/22 , Y02D10/26 , Y02D50/20
Abstract: Embodiments of an apparatus for improving performance for events handling are presented. In one embodiment, the apparatus includes a number of processing elements and task routing logic. If at least one of the processing elements is in a turbo mode, the task routing logic selects a processing element for executing a task based at least on a comparison of performance losses.
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公开(公告)号：US09766683B2
公开(公告)日：2017-09-19
申请号：US15270206
申请日：2016-09-20
Applicant: Intel Corporation
Inventor： Shaun M. Conrad , William Knolla , Douglas R. Moran , Sm M. Rahman , Jawad Haj-Yihia , Alon Naveh , Ohad Falik
CPC classification number: G06F1/3206 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F13/40 , G06F13/4027 , G06F13/4068 , Y02D10/126 , Y02D10/128 , Y02D10/151 , Y02D10/172
Abstract: A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to provide a first uni-directional communication path for communication of first power management data from the processor to the peripheral controller. Other embodiments are described and claimed.
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公开(公告)号：US09721569B2
公开(公告)日：2017-08-01
申请号：US14722489
申请日：2015-05-27
Applicant: INTEL CORPORATION
Inventor： Ohad Falik , Michael E Deisher , Ioannis Yannis Schoinas , Jenny Chang , Hai Ming Khor
CPC classification number: G10L15/285 , G10L15/14
Abstract: Systems, apparatus and methods are described including operations for memory access via direct memory access engines, of a Gaussian Mixture Model Accelerator, corresponding to individual data streams.
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Patent Agency Ranking
公开(公告)号：US09535838B2
公开(公告)日：2017-01-03
申请号：US13691106
申请日：2012-11-30
Applicant: Intel Corporation
Inventor： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
CPC classification number: G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。
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公开(公告)号：US09477627B2
公开(公告)日：2016-10-25
申请号：US13727052
申请日：2012-12-26
Applicant: Intel Corporation
Inventor： Shaun M. Conrad , William Knolla , Douglas R. Moran , SM M. Rahman , Jawad Haj-Yihia , Alon Naveh , Ohad Falik
CPC classification number: G06F1/3206 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F13/40 , G06F13/4027 , G06F13/4068 , Y02D10/126 , Y02D10/128 , Y02D10/151 , Y02D10/172
Abstract: A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to provide a first uni-directional communication path for communication of first power management data from the processor to the peripheral controller. Other embodiments are described and claimed.
Abstract translation: 处理器包括至少一个核心，功率控制单元和与外围控制器耦合的第一互连。 第一互连是提供用于从处理器到外围控制器的第一电力管理数据的通信的第一单向通信路径。 描述和要求保护其他实施例。
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公开(公告)号：US20160188504A1
公开(公告)日：2016-06-30
申请号：US14800419
申请日：2015-07-15
Applicant: Intel Corporation
Inventor： Rajesh Sankaran Madukkarumukumana , Gilbert Neiger , Ohad Falik , Sridhar Muthrasanallur , Gideon Gerzon
IPC: G06F13/24
CPC classification number: G06F13/24 , G06F9/4812
Abstract: Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure.
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29.发明授权公开(公告)号：US09164917B2
公开(公告)日：2015-10-20
申请号：US14455147
申请日：2014-08-08
Applicant: Intel Corporation
Inventor： Ohad Falik , Ben-Zion Friedman , Jacob Doweck , Eliezer Weissmann , James B Crossland
CPC classification number: G06F12/1009 , G06F12/10 , G06F12/1027 , G06F12/1036 , G06F2212/1016 , G06F2212/507 , G06F2212/65 , G06F2212/657 , G06F2212/68
Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.
Abstract translation: 本发明的实施例一般涉及用于线性到物理地址转换的系统，方法和装置，其支持页面属性。 在一些实施例中，系统接收将存储器指针转换为存储器位置的物理存储器地址的指令。 系统可以返回物理内存地址和一个或多个页面属性。 描述和要求保护其他实施例。
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30.发明申请公开(公告)号：US20150253833A1
公开(公告)日：2015-09-10
申请号：US14716326
申请日：2015-05-19
Applicant: Intel Corporation
Inventor： Ryan D. Wells , Ohad Falik , Jose P. Allarey
IPC: G06F1/32
CPC classification number: G06F1/324 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/3234 , G06F1/3237 , G06F1/3243 , G06F1/3246 , G06F1/3287 , G06F1/329 , G06F1/3293 , G06F1/3296 , G06F9/5027 , G06F9/5094 , G06F2209/501 , Y02D10/126 , Y02D10/17 , Y02D10/171 , Y02D10/22 , Y02D10/26 , Y02D50/20
Abstract: Embodiments of an apparatus for improving performance for events handling are presented. In one embodiment, the apparatus includes a number of processing elements and task routing logic. If at least one of the processing elements is in a turbo mode, the task routing logic selects a processing element for executing a task based at least on a comparison of performance losses.
Abstract translation: 介绍了一种改善事件处理性能的装置的实施例。 在一个实施例中，该装置包括多个处理元件和任务布线逻辑。 如果至少一个处理元件处于turbo模式，则任务路由逻辑至少基于性能损失的比较来选择用于执行任务的处理元件。
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