公开(公告)号：US10170185B2

公开(公告)日：2019-01-01

申请号：US15036761

申请日：2013-12-24

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Ian A. Young

IPC: G11C14/00 ,  B82Y10/00 ,  G11C11/16 ,  G11C13/00 ,  H01L27/108 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H04L9/08

Abstract: Described is an apparatus for a hybrid eDRAM and MRAM memory cell comprising: a capacitor having a first terminal and a second terminal; a first transistor having a gate terminal coupled to a first word line (WL), a source/drain terminal coupled to bit line (BL), and drain/source terminal coupled to the first terminal of the capacitor; a resistive memory element having a first terminal and a second terminal, the first terminal of the resistive memory element device coupled to the first terminal of the capacitor; and a second transistor having a gate terminal coupled to a second WL, a source/drain terminal coupled to source line (SL), and drain/source terminal coupled to the second terminal of the resistive memory element device.

公开(公告)号：US20180331281A1

公开(公告)日：2018-11-15

申请号：US16046189

申请日：2018-07-26

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Elijah Ilya Karpov ,  Brian Doyle ,  Dmitri E. Nikonov ,  Ian Young

IPC: H01L45/00 ,  G11C14/00 ,  G11C11/16 ,  H01L27/24 ,  H01L27/02 ,  G11C13/00 ,  G11C11/00 ,  G11C8/16 ,  G06F12/02

CPC classification number: H01L45/00 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C8/16 ,  G11C11/005 ,  G11C11/16 ,  G11C13/0007 ,  G11C13/0026 ,  G11C14/0018 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/0207 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

Abstract: Some embodiments include apparatuses and methods having a memory element included in a non-volatile memory cell, a transistor, an access line coupled to a gate to the transistor, a first conductive line, and a second conductive line. The memory element can include a conductive oxide material located over a substrate and between the first and second conductive lines. The memory element includes a portion coupled to a drain of the transistor and another portion coupled to the second conductive line. The first conductive line is coupled to a source of the transistor and can be located between the access line and the memory element. The access line has a length extending in a first direction and can be located between the substrate and the memory element. The first and second conductive lines have lengths extending in a second direction.

公开(公告)号：US20180240964A1

公开(公告)日：2018-08-23

申请号：US15751102

申请日：2015-09-10

Applicant: Intel Corporation

Inventor： Dmitri E. Nikonov ,  Sasikanth Manipatruni ,  Anurag Chaudhry ,  Ian A. Young

IPC: H01L43/04 ,  H01L43/08 ,  H01L43/10 ,  H01L43/06 ,  H03K19/18

CPC classification number: H01L43/04 ,  H01L43/065 ,  H01L43/08 ,  H01L43/10 ,  H03K19/18

Abstract: Described is an apparatus which comprises: a first non-magnetic conductor; a first spin orbit coupling (SOC) layer coupled to the first non-magnetic conductor; a first ferromagnet (FM) coupled to the SOC layer; a second FM; and an insulating FM sandwiched between the first and second FMs.

公开(公告)号：US10043971B2

公开(公告)日：2018-08-07

申请号：US14546061

申请日：2014-11-18

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Elijah Ilya Karpov ,  Brian Doyle ,  Dmitri E. Nikonov ,  Ian Young

IPC: H01L45/00 ,  G06F12/02 ,  G11C14/00 ,  G11C11/16 ,  G11C8/16 ,  G11C11/00 ,  G11C13/00 ,  H01L27/02 ,  H01L27/24

Abstract: Some embodiments include apparatuses and methods having a memory element included in a non-volatile memory cell, a transistor, an access line coupled to a gate to the transistor, a first conductive line, and a second conductive line. The memory element can include a conductive oxide material located over a substrate and between the first and second conductive lines. The memory element includes a portion coupled to a drain of the transistor and another portion coupled to the second conductive line. The first conductive line is coupled to a source of the transistor and can be located between the access line and the memory element. The access line has a length extending in a first direction and can be located between the substrate and the memory element. The first and second conductive lines have lengths extending in a second direction.

公开(公告)号：US11751404B2

公开(公告)日：2023-09-05

申请号：US16141025

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Gregory Chen ,  Phil Knag ,  Ram Krishnamurthy ,  Raghavan Kumar ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Huseyin Sumbul ,  Ian A. Young

IPC: H01L27/24 ,  H10B63/00 ,  H01L29/78 ,  H01L29/66 ,  H10N70/00

CPC classification number: H10B63/30 ,  H01L29/66795 ,  H01L29/785 ,  H10N70/021 ,  H10N70/826 ,  H10N70/882 ,  H10N70/8833

Abstract: Embodiments herein describe techniques for a semiconductor device including a RRAM memory cell. The RRAM memory cell includes a FinFET transistor and a RRAM storage cell. The FinFET transistor includes a fin structure on a substrate, where the fin structure includes a channel region, a source region, and a drain region. An epitaxial layer is around the source region or the drain region. A RRAM storage stack is wrapped around a surface of the epitaxial layer. The RRAM storage stack includes a resistive switching material layer in contact and wrapped around the surface of the epitaxial layer, and a contact electrode in contact and wrapped around a surface of the resistive switching material layer. The epitaxial layer, the resistive switching material layer, and the contact electrode form a RRAM storage cell. Other embodiments may be described and/or claimed.

公开(公告)号：US11600659B2

公开(公告)日：2023-03-07

申请号：US17399530

申请日：2021-08-11

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: A three dimensional (3D) array of magnetic random access memory (MRAM) bit-cells is described, wherein the array includes a mesh of: a first interconnect extending along a first axis; a second interconnect extending along a second axis; and a third interconnect extending along a third axis, wherein the first, second and third axes are orthogonal to one another, and wherein a bit-cell of the MRAM bit-cells includes: a magnetic junction device including a first electrode coupled to the first interconnect; a piezoelectric (PZe) layer adjacent to a second electrode, wherein the second electrode is coupled to the second interconnect; and a first layer adjacent to the PZe layer and the magnetic junction, wherein the first layer is coupled the third interconnect.

公开(公告)号：US11594673B2

公开(公告)日：2023-02-28

申请号：US16367129

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Angeline Smith ,  Tanay Gosavi ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Kevin O'Brien ,  Benjamin Buford ,  Tofizur Rahman ,  Rohan Patil ,  Nafees Kabir ,  Michael Christenson ,  Ian Young ,  Hui Jae Yoo ,  Christopher Wiegand

IPC: H01F10/32 ,  H01L43/10 ,  G11C11/16 ,  H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01F41/34

Abstract: A memory device includes a first electrode including a spin-orbit material, a magnetic junction on a portion of the first electrode and a first structure including a dielectric on a portion of the first electrode. The first structure has a first sidewall and a second sidewall opposite to the first sidewall. The memory device further includes a second structure on a portion of the first electrode, where the second structure has a sidewall adjacent to the second sidewall of the first structure. The memory device further includes a first conductive interconnect above and coupled with each of the magnetic junction and the second structure and a second conductive interconnect below and coupled with the first electrode, where the second conductive interconnect is laterally distant from the magnetic junction and the second structure.

公开(公告)号：US11581417B2

公开(公告)日：2023-02-14

申请号：US16130903

申请日：2018-09-13

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Uygar Avci ,  Sou-Chi Chang ,  Ian Young

IPC: G11C11/22 ,  H01L29/51 ,  H01L29/78 ,  H01L27/11585 ,  H01L27/11502

Abstract: A capacitor is provided which comprises: a first structure comprising metal; a second structure comprising metal; and a third structure between the first and second structures, wherein the third structure comprises an improper ferroelectric material. In some embodiments, a field effect transistor (FET) is provided which comprises: a substrate; a source and drain adjacent to the substrate; and a gate stack between the source and drain, wherein the gate stack includes: a dielectric; a first structure comprising improper ferroelectric material, wherein the first structure is adjacent to the dielectric; and a second structure comprising metal, wherein the second structure is adjacent to the first structure.

公开(公告)号：US11502188B2

公开(公告)日：2022-11-15

申请号：US16009110

申请日：2018-06-14

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sasikanth Manipatruni ,  Dmitri Nikonov ,  Ian A. Young ,  Benjamin Buford ,  Tanay Gosavi ,  Kaan Oguz ,  John J. Plombon

IPC: H01L29/66 ,  H03K19/18 ,  H01L43/06 ,  H01F10/32 ,  H01F41/30 ,  H03K19/0944 ,  H01L27/02 ,  B82Y25/00

Abstract: An apparatus is provided to improve spin injection efficiency from a magnet to a spin orbit coupling material. The apparatus comprises: a first magnet; a second magnet adjacent to the first magnet; a first structure comprising a tunneling barrier; a third magnet adjacent to the first structure; a stack of layers, a portion of which is adjacent to the third magnet, wherein the stack of layers comprises spin-orbit material; and a second structure comprising magnetoelectric material, wherein the second structure is adjacent to the first magnet.

公开(公告)号：US11476412B2

公开(公告)日：2022-10-18

申请号：US16012672

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Noriyuki Sato ,  Kevin O'Brien ,  Benjamin Buford ,  Christopher Wiegand ,  Angeline Smith ,  Tofizur Rahman ,  Ian Young

IPC: H01L43/04 ,  H01L43/10 ,  H01L43/08 ,  G11C11/16 ,  G11C11/18 ,  H01F10/32 ,  B82Y25/00

Abstract: An apparatus is provided which comprises: a magnetic junction including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device; a second structure comprising one of a dielectric or metal; a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; a fourth structure comprising an antiferromagnetic (AFM) material, the fourth structure adjacent to the third structure; a fifth structure comprising a magnet with PMA, the fifth structure adjacent to the fourth structure; and an interconnect adjacent to the first structure, the interconnect comprising spin orbit material.