公开(公告)号：US08900418B2

公开(公告)日：2014-12-02

申请号：US13677126

申请日：2012-11-14

Applicant: Intermolecular, Inc.

Inventor： Imran Hashim ,  Hanhong Chen ,  Tony Chiang ,  Indranil De ,  Nobi Fuchigami ,  Edward Haywood ,  Pragati Kumar ,  Sandra Malhotra ,  Sunil Shanker

IPC: C23C14/34 ,  B05D5/12 ,  H01L49/02 ,  C23C16/40 ,  C23C16/455 ,  H01L21/314 ,  H01L21/316 ,  H01L27/108 ,  H01L21/02

CPC classification number: H01L28/65 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/02697 ,  H01L21/3141 ,  H01L21/31604 ,  H01L27/10852 ,  H01L28/40

Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.

Abstract translation: 本公开内容提供（a）制造基于钇和钛的氧化物层（例如电介质层）的方法，以具有高介电常数和低泄漏特性，以及（b）相关的器件和结构。 具有钇和钛的氧化物层可以制成无定形氧化物或交替的单层系列。 在几个实施方案中，氧化物的特征在于对特定控制的总金属的钇贡献。 如果需要，可以通过PVD工艺或者通过使用特定的前体材料以允许钛和钇的共同工艺温度窗口的原子层沉积工艺，作为反应过程的结果来生产氧化物层 反应。

公开(公告)号：US08871621B2

公开(公告)日：2014-10-28

申请号：US13722885

申请日：2012-12-20

Applicant: Intermolecular, Inc.

Inventor： Venkat Ananthan ,  Imran Hashim ,  Prashant B. Phatak

IPC: H01L21/20 ,  H01L21/36 ,  H01L49/02

CPC classification number: H01L27/2418 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L28/40 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633

Abstract: MIMCAP devices are provided that can be suitable for memory device applications, such as current selector devices for cross point memory array. The MIMCAP devices can have lower thermal budget as compared to Schottky diodes and controllable lower barrier height and lower series resistance as compared to MIMCAP tunneling diodes. The MIMCAP diode can include a low defect dielectric layer, a high defect dielectric layer, sandwiched between two electrodes having different work function values.

Abstract translation: 提供了可适用于存储器件应用的MIMCAP器件，例如用于交叉点存储器阵列的电流选择器装置。 与MIMCAP隧道二极管相比，MIMCAP器件与肖特基二极管相比可以具有更低的热量预算，并且可控制的较低势垒高度和较低的串联电阻。 MIMCAP二极管可以包括夹在具有不同功函数值的两个电极之间的低缺陷电介质层，高缺陷电介质层。

公开(公告)号：US08859299B2

公开(公告)日：2014-10-14

申请号：US13716396

申请日：2012-12-17

Applicant: Intermolecular, Inc.

Inventor： Imran Hashim

IPC: H01L21/00 ,  H01L43/12

CPC classification number: H01L43/12

Abstract: In some embodiments, HPC techniques are applied to the screening and evaluating the materials, process parameters, process sequences, and post deposition treatment processes for the development of STT-RAM stacks. Simple test structures are employed for initial screening of basic materials properties of candidate materials for each layer within the stack. The use of multiple site-isolated regions on a single substrate allows many material and/or process conditions to be evaluated in a timely and cost effective manner. Interactions between the layers as well as interactions with the substrate can be investigated in a straightforward manner.

Abstract translation: 在一些实施例中，HPC技术被应用于筛选和评估用于开发STT-RAM堆栈的材料，工艺参数，工艺顺序和后沉积处理过程。 使用简单的测试结构来初步筛选堆叠内每层的候选材料的基本材料性质。 在单个基板上使用多个位置隔离区域允许以及时和成本有效的方式评估许多材料和/或工艺条件。 可以以直接的方式研究层之间的相互作用以及与基底的相互作用。

公开(公告)号：US20140183439A1

公开(公告)日：2014-07-03

申请号：US13728860

申请日：2012-12-27

Applicant: INTERMOLECULAR, INC.

Inventor： Imran Hashim ,  Venkat Ananthan ,  Tony P. Chiang ,  Prashant B. Phatak

IPC: H01L29/872 ,  H01L29/66 ,  H01L27/24

CPC classification number: H01L27/2418 ,  H01L27/2409 ,  H01L29/872 ,  H01L45/10

Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a high leakage dielectric layer sandwiched between two lower leakage dielectric layers. The low leakage layers can function to restrict the current flow across the selector device at low voltages. The high leakage dielectric layer can function to enhance the current flow across the selector device at high voltages.

Abstract translation: 可适用于存储器件应用的选择器器件可在低电压下具有低漏电流，以减少非选定器件的漏电流路径，以及高电压下的高泄漏电流，以最大限度地减少器件切换期间的电压降。 在一些实施例中，选择器装置可以包括第一电极，三层电介质层和第二电极。 三层电介质层可以包括夹在两个较低的漏电介质层之间的高泄漏电介质层。 低泄漏层可以起到限制低电压下选择器装置的电流的作用。 高泄漏电介质层可以用于在高电压下增强选择器装置上的电流。

公开(公告)号：US08737036B2

公开(公告)日：2014-05-27

申请号：US13657782

申请日：2012-10-22

Applicant: Intermolecular, Inc.

Inventor： Hanhong Chen ,  Nobumichi Fuchigami ,  Imran Hashim ,  Edward L. Haywood ,  Pragati Kumar ,  Sandra G. Malhotra ,  Monica Sawkar Mathur ,  Prashant B. Phatak ,  Sunil Shanker

IPC: H01G4/30

CPC classification number: H01G4/1218 ,  C23C16/405 ,  C23C16/45531 ,  C23C16/56 ,  H01G4/33 ,  H01L21/02186 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02312 ,  H01L21/02337 ,  H01L21/3141 ,  H01L21/3142 ,  H01L28/40

Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO2 dielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiO2 dielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle. The process provides high deposition rates, and the resulting MIM structure has substantially no x-ray diffraction peaks associated with anatase-phase titanium oxide.

Abstract translation: 本公开内容提供（a）制造基于氧化钛的氧化物层（例如电介质层）的方法，以抑制锐钛矿相氧化钛的形成和（b）相关的器件和结构。 使用底部电极（或其他基底）的臭氧预处理随后进行ALD工艺来形成金属 - 绝缘体 - 金属（“MIM”）堆叠，以形成根植于使用含酰胺的前体的TiO 2电介质。 在ALD工艺之后，氧化退火工艺的应用热度足以愈合TiO2电介质中的缺陷，并降低TiO2和电极之间的界面态; 选择退火温度以使其不那么热，以致破坏BEL表面粗糙度。 进一步的工艺变型可以包括在ALD工艺期间掺杂氧化钛，基座加热至275-300摄氏度，对于BEL使用铂或钌，对于每个ALD工艺循环使用多个试剂脉冲的臭氧。 该方法提供高沉积速率，并且所得MIM结构基本上没有与锐钛矿相氧化钛相关的x射线衍射峰。

公开(公告)号：US20140117303A1

公开(公告)日：2014-05-01

申请号：US13722314

申请日：2012-12-20

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim ,  Tim Minvielle ,  Dipankar Pramanik ,  Takeshi Yamaguchi

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/56 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

Abstract: Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from alloys of transition metals. Some examples of such alloys include chromium containing alloys that may also include nickel, aluminum, and/or silicon. Other examples include tantalum and/or titanium containing alloys that may also include a combination of silicon and carbon or a combination of aluminum and nitrogen. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature processing. In some embodiments, the breakdown voltage of a current limiting layer is at least about 8V. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layers while maintaining their performance.

公开(公告)号：US08652923B2

公开(公告)日：2014-02-18

申请号：US13829194

申请日：2013-03-14

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim

IPC: H01L21/20

CPC classification number: H01L45/1608 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/065 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625

Abstract: Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.

Abstract translation: 本发明的实施例一般涉及具有设置在至少一个电极和形成在非易失性存储器件中的可变电阻层之间的界面层结构的电阻式开关非易失性存储器件及其形成方法。 通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。 在电阻式开关非易失性存储器件的一种结构中，界面层结构包括钝化区域，界面耦合区域和/或可变电阻层接口区域，其被配置为调整非易失性存储器件的性能，例如降低形成 器件的开关电流并降低器件的成型电压，并降低从一个成形器件到另一个器件的性能变化。

公开(公告)号：US08633039B2

公开(公告)日：2014-01-21

申请号：US13932640

申请日：2013-07-01

Applicant: Intermolecular, Inc.

Inventor： Gaurav Verma ,  Tony P. Chiang ,  Imran Hashim ,  Sandra G. Malhotra ,  Prashant B. Phatak ,  Kurt H. Weiner

IPC: H01L21/00

CPC classification number: G01R31/2831 ,  G01R31/2834 ,  H01L22/34

Abstract: In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

Abstract translation: 在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。 这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。 通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。 即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。 测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。

公开(公告)号：US20130334490A1

公开(公告)日：2013-12-19

申请号：US13971467

申请日：2013-08-20

Applicant: Intermolecular Inc. ,  SanDisk 3D LLC ,  Kabushiki Kaisha Toshiba

Inventor： Hieu Pham ,  Vidyut Gopal ,  Imran Hashim ,  Tim Minvielle ,  Yun Wang ,  Takeshi Yamaguchi ,  Hong Sheng Yang

IPC: H01L45/00

CPC classification number: H01L45/08 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641

Abstract: Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed. The nonvolatile memory element comprises a first electrode layer, a second electrode layer, and a plurality of layers of an oxide disposed between the first and second electrode layers. One of the oxide layers has linear resistance and substoichiometric composition, and the other oxide layer has bistable resistance and near-stoichiometric composition. Preferably, the sum of the two oxide layer thicknesses is between about 20 Å and about 100 Å, and the oxide layer with bistable resistance has a thickness between about 25% and about 75% of the total thickness. In one embodiment, the oxide layers are formed using reactive sputtering in an atmosphere with controlled flows of argon and oxygen.

公开(公告)号：US20130217179A1

公开(公告)日：2013-08-22

申请号：US13829194

申请日：2013-03-14

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/065 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625

Abstract: Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.

Abstract translation: 本发明的实施例一般涉及具有设置在至少一个电极和形成在非易失性存储器件中的可变电阻层之间的界面层结构的电阻式开关非易失性存储器件及其形成方法。 通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。 在电阻式开关非易失性存储器件的一种结构中，界面层结构包括钝化区域，界面耦合区域和/或可变电阻层接口区域，其被配置为调整非易失性存储器件的性能，例如降低形成 器件的开关电流并降低器件的成型电压，并降低从一个成形器件到另一个器件的性能变化。