公开(公告)号：US20170154775A1

公开(公告)日：2017-06-01

申请号：US15258144

申请日：2016-09-07

Applicant: International Business Machines Corporation

Inventor： KARTHIK BALAKRISHNAN ,  KANGGUO CHENG ,  POUYA HASHEMI ,  ALEXANDER REZNICEK

IPC: H01L21/02 ,  H01L21/3105 ,  H01L21/324 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L21/02694 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/28255 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/32055 ,  H01L21/324 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/7378 ,  H01L29/7848 ,  H01L29/785 ,  H01L31/1816 ,  H01L2924/10271

Abstract: A semiconductor device comprising a substrate having a region protruding from the substrate surface; a relaxed semiconductor disposed on the region; an additional semiconductor disposed on the relaxed semiconductor; and low density dielectric disposed next to and at least partially underneath the relaxed semiconductor and adjacent to the protruding region of the substrate.

公开(公告)号：US20170077256A1

公开(公告)日：2017-03-16

申请号：US14852459

申请日：2015-09-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： PRANEET ADUSUMILLI ,  HEMANTH JAGANNATHAN ,  ALEXANDER REZNICEK ,  OSCAR VAN DER STRATEN ,  CHIH-CHAO YANG

IPC: H01L29/49 ,  H01L29/66 ,  H01L27/088 ,  H01L23/528 ,  H01L23/532 ,  H01L21/28 ,  H01L29/40 ,  H01L21/768

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76897 ,  H01L21/823828 ,  H01L23/528 ,  H01L23/53209 ,  H01L27/088 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/6656

Abstract: A CMOS fabrication process provides metal gates and contact metallization protected by metal cap layers resistant to reagents employed in downstream processing. Cobalt gates and contact metallization are accordingly feasible in CMOS processing requiring downstream wet cleans and etch processes that would otherwise compromise or destroy them. Low resistivity metal cap materials can be employed.

Abstract translation: CMOS制造工艺提供金属栅极和接触金属化，其被金属盖层保护，对下游处理中使用的试剂具有抗性。 因此，钴栅极和接触金属化在CMOS加工中是可行的，需要下游的湿法清洗和蚀刻工艺，否则会损害或破坏它们。 可以采用低电阻金属帽材料。

公开(公告)号：US20160379981A1

公开(公告)日：2016-12-29

申请号：US14750455

申请日：2015-06-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： KARTHIK BALAKRISHNAN ,  KANGGUO CHENG ,  POUYA HASHEMI ,  ALEXANDER REZNICEK

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823892 ,  H01L27/0928 ,  H01L29/66795 ,  H01L29/7849

Abstract: A finned structure is fabricated using a bulk silicon substrate having a carbon-doped epitaxial silicon germanium layer. A pFET region of the structure includes fins having silicon germanium top portions and an epitaxial carbon-doped silicon germanium diffusion barrier that suppresses dopant diffusion from the underlying n-well into the silicon germanium fin region during device fabrication. The structure further includes an nFET region including silicon fins formed from the substrate. The carbon-doped silicon germanium diffusion barrier has the same or higher germanium content than the silicon germanium fins.

Abstract translation: 使用具有碳掺杂外延硅锗层的体硅衬底制造翅片结构。 该结构的pFET区域包括具有硅锗顶部部分的散热片和外延碳掺杂硅锗扩散势垒，其在器件制造期间抑制掺杂剂从底层n阱扩散到硅锗鳍区域。 该结构还包括nFET区域，其包括从该衬底形成的硅散热片。 碳掺杂硅锗扩散阻挡层具有与硅锗鳍相同或更高的锗含量。

公开(公告)号：US20140145270A1

公开(公告)日：2014-05-29

申请号：US13687515

申请日：2012-11-28

Applicant: International Business Machines Corporation

Inventor： KANGGUO CHENG ,  BRUCE B. DORIS ,  ALI KHAKIFIROOZ ,  ALEXANDER REZNICEK

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/78 ,  H01L27/088 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7849

Abstract: A method for fabricating a semiconductor device includes providing one or more gate structures over a strained semiconductor substrate. One or more spacers are formed on the gate structures. One or more notches are formed in the strained semiconductor substrate. The one or more notches are filled to provide strain relaxation in a channel region of the strained semiconductor substrate.

Abstract translation: 一种用于制造半导体器件的方法包括在应变半导体衬底上提供一个或多个栅极结构。 在栅极结构上形成一个或多个间隔物。 在应变半导体衬底中形成一个或多个凹口。 填充一个或多个凹口以在应变半导体衬底的沟道区域中提供应变松弛。