公开(公告)号：US20180047834A1

公开(公告)日：2018-02-15

申请号：US15654892

申请日：2017-07-20

Applicant: International Business Machines Corporation

Inventor： Robin Hsin-Kuo Chao ,  Michael A. Guillorn ,  Chi-Chun Liu ,  Shogo Mochizuki ,  Chun W. Yeung

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L21/306

CPC classification number: H01L29/66818 ,  H01L21/26513 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66439 ,  H01L29/66553 ,  H01L29/7853

Abstract: A method for manufacturing a semiconductor device includes forming a stacked configuration of first and second semiconductor layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, wherein the plurality of dummy gates cover a portion of the stacked configuration in a channel region, performing an implantation of a semiconductor material on exposed portions of the stacked configuration in a source/drain region, wherein the implantation increases a concentration of the semiconductor material in the exposed portions of the stacked configuration, and selectively removing first semiconductor layers having an increased concentration of the semiconductor material from the source/drain region, wherein the removed first semiconductor layers correspond in position to the first semiconductor layers in the channel region.

公开(公告)号：US20180030312A1

公开(公告)日：2018-02-01

申请号：US15728877

申请日：2017-10-10

Applicant: International Business Machines Corporation

Inventor： Joy Cheng ,  Michael A. Guillorn ,  Chi-Chun Liu ,  Jed W. Pitera ,  Hsinyu Tsai

IPC: C09D201/00 ,  H01L21/027 ,  G03F7/00

CPC classification number: C09D201/00 ,  G03F7/0002 ,  H01L21/0271

Abstract: The disclosure provides methods for directed self-assembly (DSA) of a block co-polymer (BCP). In one embodiment, a method includes: forming an oxide spacer along each of a first sidewall and a second sidewall of a cavity in a semiconductor substrate; forming a neutral layer between the oxide spacers and along a bottom of the cavity; and removing the oxide spacers to expose the first and second sidewalls and a portion of the bottom of the cavity adjacent the first and second sidewalls.

公开(公告)号：US20170371999A1

公开(公告)日：2017-12-28

申请号：US15697594

申请日：2017-09-07

Applicant: International Business Machines Corporation

Inventor： Michael A. Guillorn ,  Kafai Lai ,  Chi-Chun Liu ,  Ananthan Raghunathan ,  Hsinyu Tsai

IPC: G06F17/50 ,  H01L29/66

CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F2217/12 ,  H01L29/66795

Abstract: A method, system, and non-transitory computer readable medium for reducing chemo-epitaxy directed-self assembly (DSA) defects of a guiding pattern layout, include inserting an internal dummy between a first portion of the guiding pattern and a second portion of the guiding pattern if a vertical spacing is equal to or greater than a first predetermined distance, inserting a first external dummy along an external edge of the guiding pattern in a vertical direction if the vertical spacing is greater than a second predetermined distance, and inserting an anti-taper structure on the first external dummy if a second distance from the external edge of the guiding pattern to the edge of the first external dummy is greater than a first distance.

公开(公告)号：US09852260B2

公开(公告)日：2017-12-26

申请号：US15167247

申请日：2016-05-27

Applicant: International Business Machines Corporation

Inventor： Michael A. Guillorn ,  Kafai Lai ,  Chi-Chun Liu ,  Ananthan Raghunathan ,  Hsinyu Tsai

IPC: G06F17/50 ,  H01L29/66

CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F2217/12 ,  H01L29/66795

Abstract: A method, system, and non-transitory computer readable medium for reducing chemo-epitaxy directed-self assembly (DSA) defects of a layout of a guiding pattern, include inserting an internal dummy between a first portion of the guiding pattern and a second portion of the guiding pattern if a vertical spacing is equal to or greater than a first predetermined distance, inserting a first external dummy along an external edge of the guiding pattern in a vertical direction if the vertical spacing is greater than a second predetermined distance, and inserting an anti-taper structure on the first external dummy if a second distance from the external edge of the guiding pattern to the edge of the first external dummy is greater than a first distance.

公开(公告)号：US09847232B1

公开(公告)日：2017-12-19

申请号：US15468772

申请日：2017-03-24

Applicant: JSR CORPORATION ,  International Business Machines Corporation

Inventor： Hitoshi Osaki ,  Kristin Schmidt ,  Chi-Chun Liu

IPC: H01L21/311 ,  G03F7/11 ,  G03F7/039 ,  G03F7/16 ,  G03F7/20 ,  G03F7/32 ,  H01L21/768

CPC classification number: H01L21/76802 ,  G03F7/0002 ,  G03F7/405 ,  H01L21/3086 ,  H01L21/76832

Abstract: A pattern-forming method includes forming a base pattern having recessed portions on a front face side of a substrate. A first composition is applied on lateral faces of the recessed portions of the base pattern, to form a coating. The first composition includes a first polymer which includes on at least one end of a main chain thereof a group capable of interacting with the base pattern. A surface of the coating is contacted with a highly polar solvent. The recessed portions are filled with a second composition. The second composition includes a second polymer which is capable of forming a phase separation structure through directed self-assembly. Phase separation is permitted in the second composition to form phases. A part of the phases is removed to form a miniaturized pattern. The substrate is etched directly or indirectly using the miniaturized pattern as a mask.

公开(公告)号：US20170344694A1

公开(公告)日：2017-11-30

申请号：US15167247

申请日：2016-05-27

Applicant: International Business Machines Corporation

Inventor： Michael A. Guillorn ,  Kafai Lai ,  Chi-Chun Liu ,  Ananthan Raghunathan ,  Hsinyu Tsai

IPC: G06F17/50 ,  H01L29/66

CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F2217/12 ,  H01L29/66795

Abstract: A method, system, and non-transitory computer readable medium for reducing chemo-epitaxy directed-self assembly (DSA) defects of a layout of a guiding pattern, include inserting an internal dummy between a first portion of the guiding pattern and a second portion of the guiding pattern if a vertical spacing is equal to or greater than a first predetermined distance, inserting a first external dummy along an external edge of the guiding pattern in a vertical direction if the vertical spacing is greater than a second predetermined distance, and inserting an anti-taper structure on the first external dummy if a second distance from the external edge of the guiding pattern to the edge of the first external dummy is greater than a first distance.

公开(公告)号：US20160379837A1

公开(公告)日：2016-12-29

申请号：US14754664

申请日：2015-06-29

Applicant: International Business Machines Corporation

Inventor： Joy Cheng ,  Michael A. Guillorn ,  Chi-Chun Liu ,  Jed W. Pitera ,  Hsinyu Tsai

IPC: H01L21/308 ,  H01L21/3105 ,  C09D201/00 ,  H01L21/02

CPC classification number: C09D201/00 ,  G03F7/0002 ,  H01L21/0271

Abstract: The disclosure provides methods for directed self-assembly (DSA) of a block co-polymer (BCP). In one embodiment, a method includes: forming an oxide spacer along each of a first sidewall and a second sidewall of a cavity in a semiconductor substrate; forming a neutral layer between the oxide spacers and along a bottom of the cavity; and removing the oxide spacers to expose the first and second sidewalls and a portion of the bottom of the cavity adjacent the first and second sidewalls.

Abstract translation: 本公开提供了嵌段共聚物（BCP）的定向自组装（DSA）的方法。 在一个实施例中，一种方法包括：沿着半导体衬底中的空腔的第一侧壁和第二侧壁中的每一个形成氧化物间隔物; 在所述氧化物间隔物和所述空腔的底部之间形成中性层; 以及去除所述氧化物间隔物以暴露所述第一和第二侧壁以及邻近所述第一和第二侧壁的所述腔的底部的一部分。

公开(公告)号：US20160358820A1

公开(公告)日：2016-12-08

申请号：US15239178

申请日：2016-08-17

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc.

Inventor： Shyng-Tsong Chen ,  Cheng Chi ,  Chi-Chun Liu ,  Sylvie M. Mignot ,  Yann A. Mignot ,  Hosadurga K. Shobha ,  Terry A. Spooner ,  Wenhui Wang ,  Yongan Xu

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329

Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

Abstract translation: 提供了形成通孔到半导体器件的下层的方法。 该方法可以包括使用侧壁图像转移过程在下层上形成柱。 介电层形成在柱和下层之上; 以及图案化在所述电介质层上的通孔掩模，所述通孔掩模具有至少部分地与所述支柱重叠的掩模开口。 使用通孔掩模在电介质层中蚀刻通孔开口，掩模开口在第一方向上限定通孔开口的第一横向尺寸，并且柱沿不同于第一方向的第二方向限定通孔开口的第二横向尺寸 方向。 通孔开口填充有导体以形成通孔。 还提供了半导体器件和通孔结构。

公开(公告)号：US20160320701A1

公开(公告)日：2016-11-03

申请号：US14697669

申请日：2015-04-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Joy Cheng ,  Matthew E. Colburn ,  Chi-Chun Liu

IPC: G03F7/039 ,  H01L21/308 ,  G03F7/40

CPC classification number: G03F7/039 ,  G03F7/0002 ,  G03F7/40 ,  G03F7/405 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/3086

Abstract: A patterned photoresist is provided atop a substrate. A hardening agent is applied to the patterned photoresist to provide a polymeric coated patterned photoresist. The polymeric coated patterned photoresist is baked to provide a hardened photoresist, and subsequent the baking step, the polymeric coating is removed from the hardened photoresist by rinsing. The hardened photoresist can be removed anytime during the patterning of the substrate by an aqueous resist developer.

Abstract translation: 图案化的光致抗蚀剂被提供在衬底顶部。 将硬化剂施加到图案化的光致抗蚀剂以提供聚合物涂覆的图案化的光致抗蚀剂。 将聚合物涂覆的图案化光刻胶烘烤以提供硬化的光致抗蚀剂，随后在烘烤步骤中，通过冲洗将聚合物涂层从硬化的光致抗蚀剂中除去。 在通过含水抗蚀剂显影剂对基材图案化期间，可以随时去除硬化的光致抗蚀剂。

公开(公告)号：US09123658B2

公开(公告)日：2015-09-01

申请号：US14327968

申请日：2014-07-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jassem A. Abdallah ,  Matthew E. Colburn ,  Steven J. Holmes ,  Chi-Chun Liu

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L21/3086 ,  G03F7/0002 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3081

Abstract: A method for defining a template for directed self-assembly (DSA) materials includes patterning a resist on a stack including an ARC and a mask formed over a hydrophilic layer. A pattern is formed by etching the ARC and the mask to form template lines which are trimmed to less than a minimum feature size (L). Hydrophobic spacers are formed on the template lines and include a fractional width of L. A neutral brush layer is grafted to the hydrophilic layer. A DSA material is deposited between the spacers and annealed to form material domains in a form of alternating lines of a first and a second material wherein the first material in contact with the spacers includes a width less than a width of the lines. A metal is added to the domains forming an etch resistant second material. The first material and the spacers are removed to form a DSA template pattern.

Abstract translation: 用于定义用于定向自组装（DSA）材料的模板的方法包括在包括ARC和在亲水层上形成的掩模的堆叠上构图抗蚀剂。 通过蚀刻ARC和掩模形成图案，以形成修剪成小于最小特征尺寸（L）的模板线。 在模板线上形成疏水间隔物，并包括L的分数宽度。将中性刷层接枝到亲水层。 DSA材料沉积在间隔物之间​​并退火以形成第一和第二材料的交替线形式的材料区域，其中与间隔物接触的第一材料包括小于线宽度的宽度。 向形成耐蚀刻第二材料的区域中加入金属。 去除第一材料和间隔物以形成DSA模板图案。