公开(公告)号：US09330962B2

公开(公告)日：2016-05-03

申请号：US14457176

申请日：2014-08-12

Applicant: International Business Machines Corporation

Inventor： Chiahsun Tseng ,  David V. Horak ,  Chun-chen Yeh ,  Yunpeng Yin

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/033 ,  H01L21/3213 ,  H01L29/06 ,  H01L45/00 ,  H01L21/02 ,  H01L23/498

CPC classification number: H01L21/768 ,  H01L21/02244 ,  H01L21/02247 ,  H01L21/02249 ,  H01L21/02252 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/498 ,  H01L29/0692 ,  H01L45/1691 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal layer is deposited over a material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation or nitridation. A hard mask portion is formed over the metal layer. A plasma impermeable spacer is formed on at least one first sidewall of the hard mask portion, while at least one second sidewall of the hard mask portion is physically exposed. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. A sequence of a surface pull back of the hard mask portion, cavity etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a hole pattern having a spacing that is not limited by lithographic minimum dimensions.

公开(公告)号：US20160079384A1

公开(公告)日：2016-03-17

申请号：US14953908

申请日：2015-11-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/4966 ,  H01L21/0337 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: In one embodiment, a semiconductor device is provided that includes a gate structure present on a channel portion of a fin structure. The gate structure includes a dielectric spacer contacting a sidewall of a gate dielectric and a gate conductor. Epitaxial source and drain regions are present on opposing sidewalls of the fin structure, wherein surfaces of the epitaxial source region and the epitaxial drain region that is in contact with the sidewalls of the fin structure are aligned with an outside surface of the dielectric spacer. In some embodiments, the dielectric spacer, the gate dielectric, and the gate conductor of the semiconductor device are formed using a single photoresist mask replacement gate sequence.

公开(公告)号：US20150228762A1

公开(公告)日：2015-08-13

申请号：US14175441

申请日：2014-02-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/4966 ,  H01L21/0337 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: In one embodiment, a semiconductor device is provided that includes a gate structure present on a channel portion of a fin structure. The gate structure includes a dielectric spacer contacting a sidewall of a gate dielectric and a gate conductor. Epitaxial source and drain regions are present on opposing sidewalls of the fin structure, wherein surfaces of the epitaxial source region and the epitaxial drain region that is in contact with the sidewalls of the fin structure are aligned with an outside surface of the dielectric spacer. In some embodiments, the dielectric spacer, the gate dielectric, and the gate conductor of the semiconductor device are formed using a single photoresist mask replacement gate sequence.

Abstract translation: 在一个实施例中，提供一种半导体器件，其包括存在于鳍结构的沟道部分上的栅极结构。 栅极结构包括与栅极电介质的侧壁和栅极导体接触的电介质间隔物。 外延源极和漏极区域存在于鳍状结构的相对的侧壁上，其中与翅片结构的侧壁接触的外延源区域和外延漏极区域的表面与电介质间隔物的外表面对齐。 在一些实施例中，使用单个光致抗蚀剂掩模替换栅极序列形成半导体器件的电介质间隔物，栅极电介质和栅极导体。

公开(公告)号：US09041094B2

公开(公告)日：2015-05-26

申请号：US14035313

申请日：2013-09-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L29/772 ,  H01L29/06

CPC classification number: H01L29/0649 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A method for semiconductor fabrication includes patterning one or more mandrels over a semiconductor substrate, the one or more mandrels having dielectric material formed therebetween. A semiconductor layer is formed over exposed portions of the one or more mandrels. A thermal oxidation is performed to diffuse elements from the semiconductor layer into an upper portion of the one or more mandrels and concurrently oxidize a lower portion of the one or more mandrels to form the one or more mandrels on the dielectric material.

Abstract translation: 一种用于半导体制造的方法包括在半导体衬底上图形化一个或多个心轴，所述一个或多个心轴在其间形成介电材料。 在一个或多个心轴的暴露部分上形成半导体层。 执行热氧化以将元件从半导体层扩散到一个或多个心轴的上部，并且同时氧化一个或多个心轴的下部以在电介质材料上形成一个或多个心轴。

公开(公告)号：US20140374839A1

公开(公告)日：2014-12-25

申请号：US13925105

申请日：2013-06-24

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Junli Wang ,  Yunpeng Yin

IPC: H01L27/088 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device having a doped well area includes a doped substrate layer formed on a substrate portion of the semiconductor device. The doped substrate layer extends along a first direction to define a length and a second direction perpendicular to the first direction to define a width. A plurality of fins is formed on the doped substrate layer and an oxide substrate layer is formed between each fin. At least one gate is formed on the oxide substrate layer and extends across at least one fin among the plurality of fins.

Abstract translation: 具有掺杂阱区的半导体器件包括形成在半导体器件的衬底部分上的掺杂衬底层。 掺杂衬底层沿着第一方向延伸以限定垂直于第一方向的长度和第二方向以限定宽度。 在掺杂衬底层上形成多个翅片，并且在每个鳍片之间形成氧化物衬底层。 至少一个栅极形成在氧化物衬底层上并延伸穿过多个翅片中的至少一个翅片。

公开(公告)号：US20140367826A1

公开(公告)日：2014-12-18

申请号：US13916669

申请日：2013-06-13

Applicant: GLOBALFOUNDRIES, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hsueh-Chung Chen ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Ailian Zhao

IPC: H01L21/768 ,  H01L23/525

CPC classification number: H01L23/5256 ,  H01L21/76888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wafer chip and a method of designing the chip is disclosed. A first fuse is formed having a first critical dimension and a second fuse having a second critical dimension are formed in a layer of the chip. A voltage may be applied to burn out at least one of the first fuse and the second fuse. The first critical dimension of the first fuse may result from applying a first mask to the layer and applying light having a first property to the mask. The second critical dimension of the second fuse may result from applying a second mask to the layer and applying light having a second property to the mask.

Abstract translation: 公开了晶片芯片和芯片的设计方法。 形成具有第一临界尺寸的第一熔丝，并且在芯片的层中形成具有第二临界尺寸的第二熔丝。 可以施加电压以烧尽第一保险丝和第二保险丝中的至少一个。 第一保险丝的第一关键尺寸可以是将第一掩模施加到该层并且将具有第一特性的光施加到掩模。 第二保险丝的第二关键尺寸可以是将第二掩模应用于该层并且将具有第二特性的光施加到掩模。

公开(公告)号：US20140349088A1

公开(公告)日：2014-11-27

申请号：US14456212

申请日：2014-08-11

Applicant: International Business Machines Corporation

Inventor： Chiahsun Tseng ,  David V. Horak ,  Chun-chen Yeh ,  Yunpeng Yin

IPC: H01L21/308 ,  H01L21/67

CPC classification number: H01L21/3081 ,  H01L21/02244 ,  H01L21/02247 ,  H01L21/02249 ,  H01L21/02252 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/67063 ,  Y10T428/24802

Abstract: A metal layer is deposited over an underlying material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation and/or nitridation. A hard mask portion is formed over the metal layer. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. The sequence of a surface pull back of the hard mask portion, trench etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a line pattern having a spacing that is not limited by lithographic minimum dimensions.

公开(公告)号：US20140264603A1

公开(公告)日：2014-09-18

申请号：US14036759

申请日：2013-09-25

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-chen Yeh ,  Yunpeng Yin

IPC: H01L27/12

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66477 ,  H01L29/66545

Abstract: A transistor device and a method for forming a fin-shaped field effect transistor (FinFET) device, with the channel portion of the fins on buried silicon oxide, while the source and drain portions of the fins on silicon. An example method includes receiving a wafer with a silicon layer electrically isolated from a silicon substrate by a buried oxide (BOX) layer. The BOX layer is in physical contact with the silicon layer and the silicon substrate. The method further comprises implanting a well in the silicon substrate and forming vertical sources and drains over the well between dummy gates. The vertical sources and drains extend through the BOX layer, fins, and a portion of the dummy gates.

Abstract translation: 一种用于形成鳍状场效应晶体管（FinFET）器件的晶体管器件和方法，其中鳍状物的沟道部分在掩埋的氧化硅上，而硅片上的鳍片的源极和漏极部分。 一种示例性方法包括接收具有通过掩埋氧化物（BOX）层与硅衬底电隔离的硅层的晶片。 BOX层与硅层和硅衬底物理接触。 该方法还包括在硅衬底中注入阱并在阱之间形成垂直源和漏极。 垂直的源极和漏极延伸穿过BOX层，鳍片和一部分虚拟栅极。

公开(公告)号：US20140167162A1

公开(公告)日：2014-06-19

申请号：US13713842

申请日：2012-12-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Chiahsun Tseng ,  Junli Wang ,  Chun-chen Yeh ,  Yunpeg Yin

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78696

Abstract: A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions.

Abstract translation: 半导体器件包括绝缘层，形成在绝缘层的上表面上的有源半导体层和形成在绝缘层上的多个鳍。 翅片形成在第一源极/漏极区域和第二源极/漏极区域之间的栅极和间隔区域中，而不延伸到第一和第二源极/漏极区域中。

公开(公告)号：US10566454B2

公开(公告)日：2020-02-18

申请号：US16032213

申请日：2018-07-11

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-chen Yeh ,  Yunpeng Yin

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/283 ,  H01L29/45 ,  H01L29/417 ,  H01L29/08 ,  H01L21/768 ,  H01L23/535 ,  H01L29/06 ,  H01L29/165

Abstract: Self-aligned contacts of a semiconductor device are fabricated by forming a metal gate structure on a portion of a semiconductor layer of a substrate. The metal gate structure contacts inner sidewalls of a gate spacer. A second sacrificial epitaxial layer is formed on a first sacrificial epitaxial layer. The first sacrificial epitaxial layer is adjacent to the gate spacer and is formed on source/drain regions of the semiconductor layer. The first and second sacrificial epitaxial layers are recessed. The recessing exposes at least a portion of the source/drain regions. A first dielectric layer is formed on the exposed portions of the source/drain regions, and over the gate spacer and metal gate structure. At least one cavity within the first dielectric layer is formed above at least one of the exposed portions of source/drain regions. At least one metal contact is formed within the at least one cavity.