公开(公告)号：US20160197078A1

公开(公告)日：2016-07-07

申请号：US15069578

申请日：2016-03-14

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L27/092 ,  H01L29/165 ,  H01L29/10 ,  H01L21/308 ,  H01L21/02 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165

Abstract: A non-planar semiconductor structure containing semiconductor fins that are isolated from an underlying bulk silicon substrate by an epitaxial semiconductor stack is provided. The epitaxial semiconductor material stack that provides the isolation includes, from bottom to top, a semiconductor punch through stop containing at least one dopant of a conductivity type which differs from the conductivity type of the particular device region that the semiconductor fin is formed in, and a semiconductor diffusion barrier layer containing no n- or p-type dopant.

Abstract translation: 提供了包含通过外延半导体堆叠与下层体硅衬底隔离的半导体鳍片的非平面半导体结构。 提供隔离的外延半导体材料堆叠包括从底部到顶部的包含至少一种导电类型的不同于形成半导体鳍片的特定器件区域的导电类型的掺杂剂的半导体冲击穿通停止器，以及 不含n型或p型掺杂剂的半导体扩散阻挡层。

公开(公告)号：US20160197077A1

公开(公告)日：2016-07-07

申请号：US15069557

申请日：2016-03-14

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165

Abstract: A non-planar semiconductor structure containing semiconductor fins that are isolated from an underlying bulk silicon substrate by an epitaxial semiconductor stack is provided. The epitaxial semiconductor material stack that provides the isolation includes, from bottom to top, a semiconductor punch through stop containing at least one dopant of a conductivity type which differs from the conductivity type of the particular device region that the semiconductor fin is formed in, and a semiconductor diffusion barrier layer containing no n- or p-type dopant.

公开(公告)号：US20160181353A1

公开(公告)日：2016-06-23

申请号：US14572974

申请日：2014-12-17

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Michael P. Chudzik ,  Aritra Dasgupta ,  Herbert L. Ho ,  Donghun Kang ,  Rishikesh Krishnan ,  Vijay Narayanan ,  Kern Rim

IPC: H01L49/02 ,  H01L23/00

CPC classification number: H01L21/02365 ,  H01G4/005 ,  H01L21/02178 ,  H01L21/02617 ,  H01L21/20 ,  H01L21/3221 ,  H01L23/26 ,  H01L27/10861 ,  H01L27/1087 ,  H01L28/60 ,  H01L28/90 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including forming an oxygen gettering layer on one side of an insulating layer of a deep trench capacitor between the insulating layer and a substrate, the oxygen gettering layer including an aluminum containing compound, and depositing an inner electrode on top of the insulating layer, the inner electrode including a metal.

Abstract translation: 一种包括在绝缘层和衬底之间的深沟槽电容器的绝缘层的一侧上形成氧吸气层的方法，所述吸氧层包括含铝化合物，并且在绝缘层的顶部上沉积内电极， 内部电极包括金属。

公开(公告)号：US09362400B1

公开(公告)日：2016-06-07

申请号：US14640382

申请日：2015-03-06

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/84

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A finFET semiconductor device includes a semiconductor-on-insulator (SOI) substrate including a buried insulator layer, a plurality of semiconductor fins on the buried insulator layer, and a gate structure covering the semiconductor fins, at least one buried stressor element embedded in the buried insulator layer, and a source/drain element on an upper surface of the at least one buried stressor element and integrally formed with at least one semiconductor fin among the plurality of semiconductor fins, the at least one buried stressor element applying a stress upon the source/drain element from therebeneath.

Abstract translation: 一种finFET半导体器件包括绝缘体上半导体（SOI）衬底，其包括掩埋绝缘体层，埋置绝缘体层上的多个半导体鳍片以及覆盖半导体鳍片的栅极结构，至少一个嵌入应力元件 埋入绝缘体层，以及在所述至少一个埋置的应力元件的上表面上的源极/漏极元件，并且与所述多个半导体鳍片中的至少一个半导体鳍片整体形成，所述至少一个埋置的应力元件在 源/漏元素。

公开(公告)号：US09293583B2

公开(公告)日：2016-03-22

申请号：US14802110

申请日：2015-07-17

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/7849 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02238 ,  H01L21/76205 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for inducing stress within the channel of a semiconductor fin structure includes forming a semiconductor fin on a substrate; forming a fin hard mask layer, multiple isolation regions, and multiple spacers, on the semiconductor fin; forming a gate structure on the semiconductor fin; and oxidizing multiple outer regions of the semiconductor fin to create oxidized stressors that induce compressive stress within the channel of the semiconductor fin. A method for inducing tensile stress within the channel of a semiconductor fin by oxidizing a central region of the semiconductor fin is also provided. Structures corresponding to the methods are also provided.

Abstract translation: 一种用于在半导体鳍片结构的沟道内引发应力的方法包括在衬底上形成半导体鳍片; 在半导体翅片上形成翅片硬掩模层，多个隔离区域和多个间隔物; 在半导体鳍片上形成栅极结构; 以及氧化半导体鳍片的多个外部区域以产生在半导体鳍片的沟道内引起压应力的氧化应激物。 还提供了通过氧化半导体鳍片的中心区域来在半导体鳍片的沟道内引起拉伸应力的方法。 还提供了与方法对应的结构。

公开(公告)号：US20150333156A1

公开(公告)日：2015-11-19

申请号：US14808914

申请日：2015-07-24

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Bruce B. Doris ,  Ali Khakifirooz ,  Edward J. Nowak ,  Kern Rim

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/785

Abstract: An array of stacks containing a semiconductor fins and an oxygen-impermeable cap is formed on a semiconductor substrate with a substantially uniform areal density. Oxygen-impermeable spacers are formed around each stack, and the semiconductor substrate is etched to vertically extend trenches. Semiconductor sidewalls are physically exposed from underneath the oxygen-impermeable spacers. The oxygen-impermeable spacers are removed in regions in which semiconductor fins are not needed. A dielectric oxide material is deposited to fill the trenches. Oxidation is performed to convert a top portion of the semiconductor substrate and semiconductor fins not protected by oxygen-impermeable spacers into dielectric material portions. Upon removal of the oxygen-impermeable caps and remaining oxygen-impermeable spacers, an array including semiconductor fins and dielectric fins is provided. The dielectric fins alleviate variations in the local density of protruding structures, thereby reducing topographical variations in the height of gate level structures to be subsequently formed.

公开(公告)号：US20150318180A1

公开(公告)日：2015-11-05

申请号：US14603624

申请日：2015-01-23

Applicant: International Business Machines Corporation

Inventor： Kern Rim ,  Junli Wang

IPC: H01L21/308 ,  H01L27/12 ,  H01L23/29 ,  H01L21/84

CPC classification number: H01L29/0649 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/845 ,  H01L23/291 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for preventing damage to the insulator layer of a semiconductor device during creation of fin field effect transistor (FinFET) includes obtaining a material stack having an active semiconductor layer, an insulator layer, and an etch stop layer between the active semiconductor layer and the insulator layer; forming a fin-array from the active semiconductor layer; patterning the fin-array; and fabricating a FinFET device from the patterned fin-array; where the etch stop layer is resistant to processes the etch stop layer is exposed to during the forming, patterning, and fabricating operations, such that the etch stop layer and the insulator layer are not damaged during the forming, patterning, and fabricating operations.

Abstract translation: 在形成鳍状场效应晶体管（FinFET）期间防止半导体器件的绝缘体层损坏的方法包括获得在有源半导体层和有源半导体层之间具有有源半导体层，绝缘体层和蚀刻停止层的材料堆叠 绝缘层; 从有源半导体层形成鳍阵列; 图案化翅片阵列; 并从图案化的鳍阵列制造FinFET器件; 其中蚀刻停止层对成形，图案化和制造操作期间的蚀刻停止层具有耐受性，使得蚀刻停止层和绝缘体层在成形，图案化和制造操作期间不被损坏。

公开(公告)号：US09117875B2

公开(公告)日：2015-08-25

申请号：US14155499

申请日：2014-01-15

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Kangguo Cheng ,  Bruce Doris ,  Kern Rim

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/306 ,  H01L21/324

CPC classification number: H01L21/76224 ,  H01L21/02532 ,  H01L21/3083 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: Forming a plurality of initial trenches that extend through a layer of silicon-germanium and into a substrate to define an initial fin structure comprised of a portion of the layer of germanium-containing material and a first portion of the substrate, forming sidewall spacers adjacent the initial fin structure, performing an etching process to extend the initial depth of the initial trenches, thereby forming a plurality of final trenches having a final depth that is greater than the initial depth and defining a second portion of the substrate positioned under the first portion of the substrate, forming a layer of insulating material over-filling the final trenches and performing a thermal anneal process to convert at least a portion of the first or second portions of the substrate into a silicon dioxide isolation material that extends laterally under an entire width of the portion of the germanium-containing material.

Abstract translation: 形成多个初始沟槽，其延伸穿过硅 - 锗层并进入衬底以限定由锗含量材料层的一部分和衬底的第一部分组成的初始鳍结构，形成邻近 初始鳍结构，执行蚀刻处理以延长初始沟槽的初始深度，由此形成多个最终深度大于初始深度的最终沟槽，并且限定位于第一部分第一部分下方的衬底的第二部分 所述衬底形成覆盖所述最终沟槽的绝缘材料层，并执行热退火工艺，以将所述衬底的所述第一或第二部分的至少一部分转化成二氧化硅隔离材料，所述二氧化硅隔离材料横向延伸在整个宽度 含锗材料的一部分。

公开(公告)号：US20150200128A1

公开(公告)日：2015-07-16

申请号：US14155499

申请日：2014-01-15

Applicant: International Business Machines Corporation ,  Globalfoundries Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Kangguo Cheng ,  Bruce Doris ,  Kern Rim

IPC: H01L21/762 ,  H01L21/324 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L21/8234

CPC classification number: H01L21/76224 ,  H01L21/02532 ,  H01L21/3083 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: Forming a plurality of initial trenches that extend through a layer of silicon-germanium and into a substrate to define an initial fin structure comprised of a portion of the layer of germanium-containing material and a first portion of the substrate, forming sidewall spacers adjacent the initial fin structure, performing an etching process to extend the initial depth of the initial trenches, thereby forming a plurality of final trenches having a final depth that is greater than the initial depth and defining a second portion of the substrate positioned under the first portion of the substrate, forming a layer of insulating material over-filling the final trenches and performing a thermal anneal process to convert at least a portion of the first or second portions of the substrate into a silicon dioxide isolation material that extends laterally under an entire width of the portion of the germanium-containing material.

Abstract translation: 形成多个初始沟槽，其延伸穿过硅 - 锗层并进入衬底以限定由锗含量材料层的一部分和衬底的第一部分组成的初始鳍结构，形成邻近 初始鳍结构，执行蚀刻处理以延长初始沟槽的初始深度，由此形成多个最终深度大于初始深度的最终沟槽，并且限定位于第一部分第一部分下方的衬底的第二部分 所述衬底形成覆盖所述最终沟槽的绝缘材料层，并执行热退火工艺，以将所述衬底的所述第一或第二部分的至少一部分转化成二氧化硅隔离材料，所述二氧化硅隔离材料横向延伸在整个宽度 含锗材料的一部分。

公开(公告)号：US08987823B2

公开(公告)日：2015-03-24

申请号：US13771255

申请日：2013-02-20

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Kern Rim ,  Ramachandra Divakaruni

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1207 ,  H01L21/845 ,  H01L27/1211

Abstract: Methods and structures for forming a localized silicon-on-insulator (SOI) finFET are disclosed. Fins are formed on a bulk substrate. Nitride spacers protect the fin sidewalls. A shallow trench isolation region is deposited over the fins. An oxidation process causes oxygen to diffuse through the shallow trench isolation region and into the underlying silicon. The oxygen reacts with the silicon to form oxide, which provides electrical isolation for the fins. The shallow trench isolation region is in direct physical contact with the fins and/or the nitride spacers that are disposed on the fins. Structures comprising bulk-type fins, SOI-type fins, and planar regions are also disclosed.

Abstract translation: 公开了用于形成局部绝缘体上硅（SOI）finFET的方法和结构。 翅片形成在块状基底上。 氮化物间隔件保护翅片侧壁。 浅沟槽隔离区域沉积在鳍片上。 氧化过程导致氧气扩散通过浅沟槽隔离区域并进入下面的硅。 氧与硅反应形成氧化物，为散热片提供电气隔离。 浅沟槽隔离区域与布置在鳍片上的翅片和/或氮化物间隔物直接物理接触。 还公开了包括体型翅片，SOI型翅片和平面区域的结构。