公开(公告)号：US20200105628A1

公开(公告)日：2020-04-02

申请号：US16145143

申请日：2018-09-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yann Mignot ,  Alan Thomas ,  Daniel Sanders ,  Dario Goldfarb ,  Nelson Felix ,  Chi-Chun Liu ,  John Arnold

IPC: H01L21/66 ,  H01L21/02 ,  H01L21/311

Abstract: An exemplary semiconductor wafer includes a lower sublayer of a first organic planarization layer (OPL) material; an upper sublayer of a second OPL material deposited onto the lower sublayer; and a detectable interface between the lower sublayer and the upper sublayer. The exemplary wafer is fabricated by depositing the lower sublayer; curing the lower sublayer; and after curing the lower sublayer, depositing the upper sublayer directly onto the lower sublayer.

公开(公告)号：US20200070151A1

公开(公告)日：2020-03-05

申请号：US16419707

申请日：2019-05-22

Applicant: International Business Machines Corporation

Inventor： Chi-Chun Liu ,  Yann Mignot ,  Joshua T. Smith ,  Bassem M. Hamieh ,  Nelson Felix ,  Robert L. Bruce

IPC: B01L3/00 ,  B81C1/00

Abstract: A microfluidic chip with a high volumetric flow rate is provided that includes at least two vertically stacked microfluidic channel layers, each microfluidic channel layer including an array of spaced apart pillars. Each microfluidic channel layer is interconnected by an inlet/outlet opening that extends through the microfluidic chip. The microfluidic chip is created without wafer to wafer bonding thus circumventing the cost and yield issues associated with microfluidic chips that are created by wafer bonding.

公开(公告)号：US10578981B2

公开(公告)日：2020-03-03

申请号：US16044629

申请日：2018-07-25

Applicant: International Business Machines Corporation

Inventor： Luciana Meli Thompson ,  Ekmini A. De Silva ,  Yasir Sulehria ,  Nelson Felix

IPC: G03F7/20 ,  H01L21/02 ,  G03F7/16 ,  C23C16/30 ,  C23C16/40 ,  C23C16/455 ,  H01L21/67 ,  H01L21/027 ,  C23C16/56

Abstract: Methods for post-lithographic inspection using an e-beam inspection tool of organic extreme ultraviolet sensitive (EUV) sensitive photoresists generally includes conformal deposition of a removable metal carboxide or metal carboxynitride onto the relief image. The conformal deposition of the metal carboxide or metal carboxynitride includes a low temperature vapor deposition process of less than about 100° C. to provide a coating thickness of less than about 5 nanometers. Subsequent to e-beam inspection, the metal carboxide or metal carboxynitride coating is removed using a wet stripping process. Once stripped, the wafer can continue on to further process fabrication without being a sacrificial wafer.

公开(公告)号：US10437951B2

公开(公告)日：2019-10-08

申请号：US15684006

申请日：2017-08-23

Applicant: International Business Machines Corporation

Inventor： Ravi K. Bonam ,  Nelson Felix ,  Scott Halle ,  Luciana Meli

IPC: G06F17/50 ,  H01L21/00 ,  H01J37/32

Abstract: A method comprises: defining a set of rules for an inspection and detection of a defect in two or more electronic devices on a semiconductor chip, the set of rules being based on a modulation transfer function providing a response as contrast versus spatial frequency of the pattern spacings of the two or more electronic devices on the semiconductor chip; generating two or more care areas for two or more pattern spacings of the electronic devices on the semiconductor chip using a hierarchical set of spacing rules; and inspecting the two or more pattern spacings of the electronic devices on the semiconductor chip for defects.

公开(公告)号：US11804401B2

公开(公告)日：2023-10-31

申请号：US17484347

申请日：2021-09-24

Applicant: International Business Machines Corporation

Inventor： Nelson Felix ,  Ekmini Anuja De Silva ,  Luciana Meli Thompson ,  Yann Mignot

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L21/76802 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31051 ,  H01L21/31144

Abstract: One or more embodiments described herein include systems, and/or methods that facilitate fabrication of a semiconductor device using a spacer lithography-etch process. According to an embodiment, a method can comprise performing a first lithography exposure and etch over a first layer of a semiconductor device, where the first lithography exposure and etch comprises forming one or more mandrels on a first region of a second layer by employing a first photoresist layer. The method can further comprise forming one or more spacers on a sidewall of the one or more mandrels and covering a second region of the second layer, where the second region is adjacent to the one or more mandrels. The method can further comprise forming a cut over a third region of the second layer and filling the third region with first material.

公开(公告)号：US11164772B2

公开(公告)日：2021-11-02

申请号：US16174666

申请日：2018-10-30

Applicant: International Business Machines Corporation

Inventor： Nelson Felix ,  Ekmini Anuja De Silva ,  Luciana Meli Thompson ,  Yann Mignot

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/311

Abstract: One or more embodiments described herein include systems, and/or methods that facilitate fabrication of a semiconductor device using a spacer lithography-etch process. According to an embodiment, a method can comprise performing a first lithography exposure and etch over a first layer of a semiconductor device, where the first lithography exposure and etch comprises forming one or more mandrels on a first region of a second layer by employing a first photoresist layer. The method can further comprise forming one or more spacers on a sidewall of the one or more mandrels and covering a second region of the second layer, where the second region is adjacent to the one or more mandrels. The method can further comprise forming a cut over a third region of the second layer and filling the third region with first material.

公开(公告)号：US11133260B2

公开(公告)日：2021-09-28

申请号：US16685192

申请日：2019-11-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chi-Chun Liu ,  John C. Arnold ,  Dominik Metzler ,  Nelson Felix ,  Ashim Dutta

IPC: H01L21/302 ,  H01L23/538 ,  H01L21/768 ,  H01L21/762 ,  H01L21/033 ,  H01L21/3213

Abstract: A method of forming a self-aligned top via is provided. The method includes forming a metallization layer on a substrate, and forming a hardmask layer on the metallization layer. The method further includes forming a pair of adjacent parallel mandrels on the hardmask layer with sidewall spacers on opposite sides of each mandrel. The method further includes forming a planarization layer on the exposed portions of the hardmask layer, mandrels, and sidewall spacers, and forming an opening in the planarization layer aligned between the adjacent parallel mandrels. The method further includes forming a spacer layer in the opening, and removing portions of the spacer layer to form a pair of spacer plugs between sections of the sidewall spacers.

公开(公告)号：US11067896B2

公开(公告)日：2021-07-20

申请号：US16716984

申请日：2019-12-17

Applicant: International Business Machines Corporation

Inventor： Cody John Murray ,  Ekmini Anuja De Silva ,  Alex Richard Hubbard ,  Karen Elizabeth Petrillo ,  Nelson Felix

IPC: G03F7/40 ,  G03F7/38 ,  H01L21/027

Abstract: A method of optimizing a lithographic process for semiconductor fabrication includes determining that a semiconductor wafer experienced a photoresist exposure delay. At least one operating parameter of a post exposure baking process is adjusted based on the semiconductor wafer having experienced the photoresist exposure delay. The post exposure baking process is performed on the semiconductor wafer utilizing the adjusted at least one operating parameter.

公开(公告)号：US20210210679A1

公开(公告)日：2021-07-08

申请号：US16735020

申请日：2020-01-06

Applicant: International Business Machines Corporation

Inventor： Chi-Chun Liu ,  Yann Mignot ,  Ekmini Anuja De Silva ,  Nelson Felix ,  John Christopher Arnold

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A method of forming a semiconductor structure includes forming a memorization layer over a substrate, forming a first self-aligned double patterning (SADP) stack including a first organic planarization layer (OPL), masking layer, set of mandrels, and set of spacers, and forming a patterned memorization layer by transferring a first pattern of the first set of spacers to the memorization layer. The method also includes forming a second SADP stack comprising a second OPL, masking layer, set of mandrels, and set of spacers, and forming an array of pillars by transferring a second pattern of the second set of spacers to the patterned memorization layer. The first and second OPL and the first and second sets of mandrels are a spin-on coated OPL material, and the memorization layer and first and second masking layers are a material configured for removal selective to the spin-on coated OPL material.

公开(公告)号：US10998192B2

公开(公告)日：2021-05-04

申请号：US16570603

申请日：2019-09-13

Applicant: International Business Machines Corporation

Inventor： Ekmini Anuja De Silva ,  Jing Guo ,  Luciana Meli ,  Nelson Felix

IPC: H01L21/033 ,  H01L21/027

Abstract: A method includes depositing a resist layer onto a hard mask layer to form a multi-layer patterning material film stack on a semiconductor substrate, directing patterning radiation onto the film stack to form a developed pattern in the resist layer and exposing the film stack to at least one gas precursor in connection with a sequential infiltration synthesis process. The film stack is configured to facilitate selective infiltration of the at least one gas precursor into the resist layer.