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    CIRCUITRY FOR ONE-TRANSISTOR SYNAPSE CELL AND OPERATION METHOD OF THE SAME
    21.
    发明申请
    CIRCUITRY FOR ONE-TRANSISTOR SYNAPSE CELL AND OPERATION METHOD OF THE SAME 审中-公开

    公开(公告)号：US20190378555A1

    公开(公告)日：2019-12-12

    申请号：US16550809

    申请日：2019-08-26

    Applicant: International Business Machines Corporation

    Inventor： Jin Ping Han ,  Xiao Sun ,  Teng Yang

    IPC: G11C11/22 ,  H03K19/177

    Abstract: Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

    POWER-EFFICIENT MIXED-SIGNAL CIRCUIT INCLUDING ANALOG MULTIPLY AND ACCUMULATE ENGINES
    25.
    发明申请
    POWER-EFFICIENT MIXED-SIGNAL CIRCUIT INCLUDING ANALOG MULTIPLY AND ACCUMULATE ENGINES 有权

    公开(公告)号：US20250077804A1

    公开(公告)日：2025-03-06

    申请号：US18458141

    申请日：2023-08-29

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Ankur Agrawal ,  Andrea Fasoli ,  Monodeep Kar ,  Kyu-hyoun Kim ,  Sergey Rylov ,  Chia-Yu Chen ,  Xiao Sun

    IPC: G06G7/32

    Abstract: A first circuit is configured to split a first integer value into a first coarse value and a first fine value, and split a second integer value into a second coarse value and a second fine value. A second circuit performs an analog multiply and accumulate (MAC) operation on the first and second coarse values to produce a first analog output, perform an analog MAC operation on the first coarse value and the second fine value to produce a second analog output, perform an analog MAC operation on the first fine value and the second coarse value to produce a third analog output, and perform an analog MAC operation on the first and second fine values together to produce a fourth analog output. A third circuit is configured to perform analog-to-digital (A/D) conversion on and combine the analog output signals to produce a reconstructed digital output signal.

    Kernel sets normalization with capacitor charge sharing
    26.
    发明授权
    Kernel sets normalization with capacitor charge sharing 有权

    公开(公告)号：US11574694B2

    公开(公告)日：2023-02-07

    申请号：US16157848

    申请日：2018-10-11

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Effendi Leobandung ,  Tayfun Gokmen ,  Xiao Sun ,  Yulong Li ,  Malte Rasch

    IPC: G11C27/00 ,  G06N3/04 ,  G06N3/063

    Abstract: A method for multiple copies of a set of multi-kernel set operations in a hardware accelerated neural network includes a word line for receiving a pixel value of an input image. A bit line communicates a modified pixel value. An analog memory cell including a first capacitor stores a first kernel weight of a first kernel in one of a plurality of kernel sets such that the pixel value is operated on by the first kernel weight to produce the modified pixel value. A charge connection connects the first capacitor to at least a second capacitor storing a second kernel weight of a related kernel of a second one of the plurality of kernel sets such that charge is shared between the first capacitor and at least the second capacitor to normalize the first kernel weight and the second kernel weight.

    MIXED PRECISION CAPABLE HARDWARE FOR TUNING A MACHINE LEARNING MODEL
    29.
    发明申请
    MIXED PRECISION CAPABLE HARDWARE FOR TUNING A MACHINE LEARNING MODEL 有权

    公开(公告)号：US20210064372A1

    公开(公告)日：2021-03-04

    申请号：US16558536

    申请日：2019-09-03

    Applicant: International Business Machines Corporation

    Inventor： Xiao Sun ,  Chia-Yu Chen ,  Naigang Wang ,  Jungwook Choi ,  Kailash Gopalakrishnan

    IPC: G06F9/30 ,  G06F7/483 ,  G06N5/04 ,  G06N20/00 ,  G06F17/18

    Abstract: An apparatus includes a memory and a processor coupled to the memory. The processor includes first and second sets of arithmetic units having first and second precision for floating-point computations, the second precision being lower than the first precision. The processor is configured to obtain a machine learning model trained in the first precision, to utilize the second set of arithmetic units to perform inference on input data, to utilize the first set of arithmetic units to generate feedback for updating parameters of the second set of arithmetic units based on the inference performed on the input data by the second set of arithmetic units, to tune parameters of the second set of arithmetic units based at least in part on the feedback generated by the first set of arithmetic units, and to utilize the second set of arithmetic units with the tuned parameters to generate inference results.

    FLOATING POINT UNIT FOR EXPONENTIAL FUNCTION IMPLEMENTATION
    30.
    发明申请
    FLOATING POINT UNIT FOR EXPONENTIAL FUNCTION IMPLEMENTATION 有权

    公开(公告)号：US20210019116A1

    公开(公告)日：2021-01-21

    申请号：US16515174

    申请日：2019-07-18

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Xiao Sun ,  Ankur Agrawal ,  Kailash Gopalakrishnan ,  Silvia Melitta Mueller ,  Kerstin Claudia Schelm

    IPC: G06F7/556 ,  G06F7/523 ,  G06F7/50 ,  G06N3/08

    Abstract: A computer-implemented method for performing an exponential calculation using only two fully-pipelined instructions in a floating point unit that includes. The method includes computing an intermediate value y′ by multiplying an input operand with a predetermined constant value. The input operand is received in floating point representation. The method further includes computing an exponential result for the input operand by executing a fused instruction. The fused instructions includes converting the intermediate value y′ to an integer representation z represented by v most significant bits (MSB), and w least significant bits (LSB). The fused instruction further includes determining exponent bits of the exponential result based on the v MSB from the integer representation z. The method further includes determining mantissa bits of the exponential result according to a piece-wise linear mapping function using a predetermined number of segments based on the w LSB from the integer representation z.

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