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    n-Bit successive approximation register analog-to-digital converter and method for calibrating the same, receiver, base station and mobile device
    22.
    发明授权
    n-Bit successive approximation register analog-to-digital converter and method for calibrating the same, receiver, base station and mobile device 有权

    公开(公告)号：US11177820B2

    公开(公告)日：2021-11-16

    申请号：US16933292

    申请日：2020-07-20

    Applicant: Intel Corporation

    Inventor： Albert Molina ,  Martin Clara ,  Matteo Camponeschi ,  Christian Lindholm ,  Kameran Azadet

    IPC: H03M1/10 ,  H04B1/16

    Abstract: A n-bit Successive Approximation Register Analog-to-Digital Converter, SAR ADC, is provided. The SAR ADC comprises a respective plurality of sampling cells for each bit of the n-bit of the SAR ADC. Each sampling cell comprises a capacitive element coupled to a cell output of the sampling cell in order to provide a cell output signal. Further, each sampling cell comprises a first cell input for receiving a first signal, and a first switch circuit capable of selectively coupling the first cell input to the capacitive element. Each cell additionally comprises a second cell input for receiving a second signal, and a third cell input for receiving a third signal. The third signal exhibits opposite polarity compared to the second signal. Each sampling cell comprises a second switch circuit capable of selectively coupling one of the second cell input and the third cell input to the capacitive element. The SAR ADC further comprises at least one comparator circuit coupled to the sampling cells. The at least one comparator circuit is configured to output a comparison signal based on the cell output signals of the sampling cells. Additionally, the SAR ADC comprises a calibration circuit configured to supply at least one respective control signal to the respective second switch circuit of the sampling cells for controlling the second switch circuits.

    n-bit successive approximation register analog-to-digital converter and method for calibrating the same, receiver, base station and mobile device
    23.
    发明授权
    n-bit successive approximation register analog-to-digital converter and method for calibrating the same, receiver, base station and mobile device 有权

    公开(公告)号：US10742225B1

    公开(公告)日：2020-08-11

    申请号：US16728226

    申请日：2019-12-27

    Applicant: Intel Corporation

    Inventor： Albert Molina ,  Martin Clara ,  Matteo Camponeschi ,  Christian Lindholm ,  Kameran Azadet

    IPC: H03M1/10 ,  H04B1/16

    Abstract: A n-bit Successive Approximation Register Analog-to-Digital Converter, SAR ADC, is provided. The SAR ADC comprises a respective plurality of sampling cells for each bit of the n-bit of the SAR ADC. Each sampling cell comprises a capacitive element coupled to a cell output of the sampling cell in order to provide a cell output signal. Further, each sampling cell comprises a first cell input for receiving a first signal, and a first switch circuit capable of selectively coupling the first cell input to the capacitive element. Each cell additionally comprises a second cell input for receiving a second signal, and a third cell input for receiving a third signal. The third signal exhibits opposite polarity compared to the second signal. Each sampling cell comprises a second switch circuit capable of selectively coupling one of the second cell input and the third cell input to the capacitive element. The SAR ADC further comprises at least one comparator circuit coupled to the sampling cells. The at least one comparator circuit is configured to output a comparison signal based on the cell output signals of the sampling cells. Additionally, the SAR ADC comprises a calibration circuit configured to supply at least one respective control signal to the respective second switch circuit of the sampling cells for controlling the second switch circuits.

    Time-interleaved analog-to-digital converter system
    25.
    发明授权
    Time-interleaved analog-to-digital converter system 有权

    公开(公告)号：US11271578B2

    公开(公告)日：2022-03-08

    申请号：US17059495

    申请日：2019-03-29

    Applicant: Intel Corporation

    Inventor： Albert Molina ,  Kameran Azadet ,  Matteo Camponeschi ,  Jose Luis Ceballos ,  Christian Lindholm

    IPC: H03M1/12 ,  H03M1/06 ,  H03M1/10

    Abstract: A time-interleaved Analog-to-Digital Converter, ADC, system is provided. The time-inter-leaved ADC system includes time-interleaved first and second ADC circuits and a switching circuit. The switching circuit is configured to selectively supply an analog input signal for digitization to at least one of the first ADC circuit, the second ADC circuit or ground, and to selectively supply an analog calibration signal to at least one of the first ADC circuit, the second ADC circuit or ground. Further, the time-interleaved ADC system includes an output circuit configured to selectively generate, based on least one of a first digital signal output by the first ADC circuit and a second digital signal output by the second ADC circuit, a digital output signal.

    Apparatus and method for time-interleaved analog-to-digital conversion
    26.
    发明授权
    Apparatus and method for time-interleaved analog-to-digital conversion 有权

    公开(公告)号：US11082054B1

    公开(公告)日：2021-08-03

    申请号：US16912812

    申请日：2020-06-26

    Applicant: Intel Corporation

    Inventor： Giacomo Cascio ,  Christian Lindholm ,  Albert Molina ,  Martin Clara

    IPC: H03M1/12 ,  H03M1/06 ,  H03M1/36

    Abstract: The present disclosure relates to a time-interleaved ADC circuit. The time-interleaved ADC circuit comprises an input for an analog input signal, a first ADC bank comprising a first plurality of parallel time-multiplexed ADCs, wherein the first plurality of parallel time-multiplexed ADCs is configured to subsequently generate a first plurality of samples of the analog input signal during a first time interval, a first buffer amplifier coupled between the input and the first ADC bank. The time-interleaved ADC circuit further comprises a second ADC bank comprising a second plurality of parallel time-multiplexed ADCs, wherein the second plurality of parallel time-multiplexed ADCs is configured to subsequently generate a second plurality of samples of the analog input signal during a second time interval, wherein the first and the second time intervals are subsequent time intervals, a second buffer amplifier coupled between the input and the second ADC bank. The first ADC bank has associated therewith a first dummy sampler, wherein the ADC circuit is configured to activate the first dummy sampler before the start of the first time interval. The second ADC bank has associated therewith a second dummy sampler, wherein the ADC circuit is configured to activate the second dummy sampler before the start of the second time interval.

    Channel estimation using peak cancellation
    29.
    发明授权
    Channel estimation using peak cancellation 有权

    公开(公告)号：US10164800B2

    公开(公告)日：2018-12-25

    申请号：US15475783

    申请日：2017-03-31

    Applicant: Intel Corporation

    Inventor： Albert Molina ,  Kameran Azadet

    IPC: H04L25/02 ,  H04L27/26 ,  H04B7/0413 ,  H04J13/00

    Abstract: An apparatus and a method for estimation a wireless channel are disclosed. For example, the method correlates, by a correlator, a plurality of signals of a combined signal received by a receive antenna over the wireless channel from a plurality of transmit antennas, with respective DMRSs of the plurality of transmit antennas, converts, by a converter, the correlated plurality of signals from frequency to time domain, iteratively peak cancels, by a peak canceller, a largest peak of the combined impulse response and stores a scaling factor and location pair of the cancelled peak until a magnitude of a next largest peak is below a predetermined threshold, assigns, by an assigner, each of the scaling factor and location pairs to a transmit antenna, and estimates, by an estimator, for each of the plurality of transmit antennas, the wireless channel based on the assigned scaling factor and location pairs.

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