公开(公告)号：US20170286358A1

公开(公告)日：2017-10-05

申请号：US15086700

申请日：2016-03-31

Applicant: INTEL CORPORATION

Inventor： Amit Kumar Srivastava

IPC: G06F13/42 ,  G06F13/364 ,  G06F13/16 ,  G06F1/32

CPC classification number: G06F13/4291 ,  G06F1/324 ,  G06F13/1673 ,  G06F13/364

Abstract: Described is an I3C Repeater. The I3C Repeater may have a first circuitry with an I3C interface, a second circuitry with an I2C interface, and a datapath circuitry coupled to the first circuitry and the second circuitry. The second circuitry may be operable to convert a transaction received on the I2C interface into a transaction for the I3C interface, and to convert a transaction received on the I3C interface into a transaction for the I2C interface. The I3C Repeater may also have additional circuitries operable to convert transactions received on one of an SPI interface, a UART interface, and a Debug bus interface into transactions for the I3C interface, and vice-versa.

公开(公告)号：US09780783B1

公开(公告)日：2017-10-03

申请号：US15087462

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava

IPC: H03K17/16 ,  H03K19/003 ,  H03K19/00 ,  H03K19/0175

CPC classification number: H03K19/0005 ,  G06F13/4072 ,  G06F13/4086 ,  H03K19/017509

Abstract: Apparatuses and methods associated with voltage tolerant termination presence detection for universal serial bus type-C connectors are disclosed herein. In embodiments, an apparatus to enable voltage tolerant termination presence detection may include sensor circuitry to determine whether a device coupled to the sensor circuitry is to operate in host mode or device mode based on a signal on a configuration channel between the device and the sensor circuitry. In embodiments, the apparatus may further include termination circuitry to bias the configuration channel in accordance with the host mode or the device mode based on the determination of whether the device is to operate in the host mode or the device mode. Other embodiments may be described and/or claimed.

公开(公告)号：US09628124B1

公开(公告)日：2017-04-18

申请号：US15239742

申请日：2016-08-17

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava

IPC: H04B5/00 ,  H04B1/10 ,  H04W4/00

CPC classification number: H04B1/1036 ,  H04B2001/1072 ,  H04W4/70

Abstract: Embodiments of the present disclosure provide techniques and configurations for an apparatus for mitigating interference in sensor signals. In one instance, the apparatus may include sensors and a processing block couplable with the sensors. The processing block may include a front end block to receive sensor signals, and tunable filter block to filter the sensor signals. The apparatus may further include a correction block. The correction block may include a replica of the front end block, and may be configured to receive interference information. A controller may operate the correction block to adjust the tunable filter block, based on interference information, and connect the sensors with the processing block after adjustment. The controller may operate the processing block, in response to connection of the processing block with the sensors, to initiate processing of sensor signals filtered by the filter block, to mitigate interference. Other embodiments may be described and/or claimed.

公开(公告)号：US09606949B1

公开(公告)日：2017-03-28

申请号：US14864019

申请日：2015-09-24

Applicant: INTEL CORPORATION

Inventor： Khang Choong Yong ,  Khai Ern See ,  Amit Kumar Srivastava ,  Jackson Chung Peng Kong ,  Teong Keat Beh ,  Eng Huat Goh

IPC: G06F3/00 ,  G06F13/38 ,  G06F13/40 ,  G06F3/06 ,  G06F11/14

CPC classification number: G06F13/385 ,  G06F3/0634 ,  G06F3/065 ,  G06F3/0673 ,  G06F11/1456 ,  G06F13/4022 ,  G06F13/4081 ,  G06F2201/84

Abstract: A universal interconnection scheme enables system architecture modularization with a hot-pluggable external computing module, such as a PC-on-a-card device using USB type-C technology. With the flexibility to interchange the system computing module with an external module, system performance can be augmented to fulfill the essential needs of the user, whether the system is a portable low-power tablet device, a smartphone, a wearable device such as an Internet of Things device, or a high-performance PC.

公开(公告)号：US09601916B2

公开(公告)日：2017-03-21

申请号：US14483649

申请日：2014-09-11

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Karthik Ns ,  Raghavendra Devappa Sharma ,  Dharmaray Nedalgi ,  Prasad Bhilawadi

IPC: G06K19/00 ,  H02H3/18

CPC classification number: H02H3/18 ,  G06F1/26 ,  G06F1/3212 ,  H04B1/38 ,  H04L25/0272

Abstract: Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.

公开(公告)号：US11996853B2

公开(公告)日：2024-05-28

申请号：US17196806

申请日：2021-03-09

Applicant: INTEL CORPORATION

Inventor： Amit Kumar Srivastava

IPC: H03L7/22 ,  G06F1/08 ,  G06F1/10 ,  G06F1/12 ,  G06F1/14 ,  H03L7/087 ,  H03L7/18 ,  H03L7/23 ,  H03L7/197 ,  H03M1/12 ,  H03M1/50

CPC classification number: H03L7/087 ,  G06F1/10 ,  G06F1/12 ,  G06F1/14 ,  H03L7/23 ,  H03L7/235 ,  H03L7/1976 ,  H03M1/1255 ,  H03M1/50

Abstract: Described is an apparatus which comprises: a first clocking source having a first divider; a second clocking source having a second divider, wherein the first and second clocking sources are inductively coupled; and calibration logic to monitor clock signals associated with the first and second clocking sources and to generate at least one calibration code for adjusting at least one divider ratio of the first or second dividers according to the monitored clock signals.

公开(公告)号：US11506702B2

公开(公告)日：2022-11-22

申请号：US17031107

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Asad Azam ,  Amit Kumar Srivastava ,  Enrico Carrieri ,  Rajesh Bhaskar

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/3185 ,  G11C29/32 ,  G11C29/46 ,  G11C29/36 ,  G11C29/08

Abstract: An apparatus of a multi-chip package (MCP) of a functional safety system, comprises a processor to be configured as a master chip in a master-slave arrangement with a slave chip in the MCP, and a memory coupled to the processor to store one or more infield test scan patterns. The processor includes a bock to couple the master chip to the slave chip via a high-speed input/output (IO) interface to retrieve the one or more infield test scan patterns from the memory via the master chip, and to provide the one or more infield test scan patterns to the slave chip via the high-speed IO interface in response to the functional safety system entering an infield test mode.

公开(公告)号：US11036266B2

公开(公告)日：2021-06-15

申请号：US16943155

申请日：2020-07-30

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Rao Jagannadha Rapeta ,  Asad Azam

IPC: G06F1/20 ,  G05B15/02

Abstract: The disclosed embodiments relate to methods, systems and apparatus for dynamic temperature aware functional safety. The disclosed embodiments provide adaptive techniques to track extended dynamic temperature range of a System-on-Chip (SOC) and automatically tune critical IP components of the SOC so that system can operate reliably even at high temperatures. The disclosed embodiments relax the overdesign of the SOC components by reusing existing components such as a ring oscillator to determine temperature at different regions of the SOC. In one embodiment, the disclosed principles use a Calibrated Ring Oscillator (CRO) temperature sensors. The CRO-based temperature sensors provide fast temperature measurement suitable for detecting dynamic temperature ranges and temperature rate of change. The CROs are existing on the SOC and do not require addition of additional sensors.

公开(公告)号：US11016550B2

公开(公告)日：2021-05-25

申请号：US16062093

申请日：2016-11-23

Applicant: INTEL CORPORATION

Inventor： Ramnarayanan Muthukaruppan ,  Anoop Kumar Upadhyay ,  Gaurav Goel ,  Amit Kumar Srivastava

IPC: G06F1/24 ,  G06F9/00 ,  G06F1/28 ,  G06F1/3287 ,  G06F13/40 ,  G06F1/3234 ,  G06F9/445 ,  G06F13/20

Abstract: A configuration interface bus may be coupled to components of a physical layer (PHY) device. A configuration controller may be coupled with the configuration interface bus and may receive an input signal representing a power state of the PHY device. The configuration controller may further identify a set of instructions that correspond to the input signal and may transmit configuration data via the configuration interface bus to one or more of the components of the PHY device in response to an execution of the set of instructions. The operation of the one or more components of the PHY device may be based on the configuration data.

公开(公告)号：US10915415B2

公开(公告)日：2021-02-09

申请号：US15776384

申请日：2016-10-13

Applicant: INTEL CORPORATION ,  Amit Kumar Srivastava ,  Huimin Chen

Inventor： Amit Kumar Srivastava ,  Huimin Chen

IPC: G06F11/00 ,  G06F11/273 ,  G06F11/22 ,  G06F13/42

Abstract: Techniques and mechanisms for exchanging debug information with a repeater and multiplex logic of a platform. In an embodiment, the multiplex logic can be configured to any of multiple modes including a first mode to exchange debug information between the repeater and debug client logic of the platform. Another of the multiple modes may provide an alternate communication path for exchanging functional data, other than any debug information, between the repeater and a physical layer interface of the platform. In another embodiment, the repeater is compatible with a repeater architecture identified by a universal serial bus standard. The physical layer interface is compatible with an interface specification identified by the same universal bus standard.