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公开(公告)号：US20170357584A1
公开(公告)日：2017-12-14
申请号：US15688209
申请日：2017-08-28
Applicant: Intel Corporation
Inventor： Sanjay K. KUMAR , Rajesh M. Sankaran , Subramanya R. Dulloor , Andrew V. Anderson
IPC: G06F12/0804 , G06F11/14
CPC classification number: G06F12/0804 , G06F9/467 , G06F11/07 , G06F11/073 , G06F11/0778 , G06F11/0793 , G06F11/14 , G06F11/1482 , G06F12/0868 , G06F2201/805 , G06F2201/82 , G06F2212/1032 , G06F2212/608
Abstract: A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the FoC instruction. The memory management unit includes logic to, based upon a flush-on-fail (FoF) mode, skip execution of the flush-on-commit instruction and to flush the dirty data from the volatile cache upon a subsequent FoF operation.
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公开(公告)号：US09715453B2
公开(公告)日：2017-07-25
申请号：US14567662
申请日：2014-12-11
Applicant: Intel Corporation
Inventor： Sanjay Kumar , Rajesh M. Sankaran , Subramanya R. Dulloor , Dheeraj R. Subbareddy , Andrew V. Anderson
IPC: G06F3/06 , G06F12/0842 , G06F12/02 , G06F12/0897 , G06F12/1009
CPC classification number: G06F12/0842 , G06F12/0238 , G06F12/06 , G06F12/0897 , G06F12/1009 , G06F2212/225 , G06F2212/601 , G06F2212/7201
Abstract: Computer-readable storage media, computing apparatuses and methods associated with persistent memory are discussed herein. In embodiments, a computing apparatus may include one or more processors, along with a plurality of persistent storage modules that may be coupled with the one or more processors. The computing apparatus may further include system software, to be operated by the one or more processors, to receive volatile memory allocation requests and persistent storage allocation requests from one or more applications that may be executed by the one or more processors. The system software may then dynamically allocate memory pages of the persistent storage modules as: volatile type memory pages, in response to the volatile memory allocation requests, and persistent type memory pages, in response to the persistent storage allocation requests. Other embodiments may be described and/or claimed.
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公开(公告)号：US09710393B2
公开(公告)日：2017-07-18
申请号：US14750982
申请日：2015-06-25
Applicant: Intel Corporation
Inventor： Michael Lemay , David M. Durham , Andrew V. Anderson , Gilbert Neiger , Ravi L. Sahita
IPC: G06F12/00 , G06F12/1009 , G06F12/1027 , G06F12/14 , G06F9/455 , G06F21/00
CPC classification number: G06F12/1009 , G06F9/45533 , G06F9/45558 , G06F12/1027 , G06F12/1483 , G06F21/00 , G06F21/53 , G06F2009/45583 , G06F2009/45587 , G06F2212/1024 , G06F2212/1052 , G06F2212/151 , G06F2212/651 , G06F2212/657 , G06F2212/68 , G06F2221/2141
Abstract: Generally, this disclosure provides systems, methods and computer readable media for a page table edit controller configured to control access to guest page tables by virtual machine (VM) guest software through the manipulation of extended page tables. The system may include a translation look-aside buffer (TLB) to maintain a policy to lock one or more guest linear addresses (GLAs) to one or more allowable guest physical addresses (GPAs); a page walk processor to update the TLB based on the guest page tables; and a page table edit control (PTEC) module to: identify entries of the guest page tables that map GLAs associated with the policy to a first GPA; verify that the mapping conforms to the policy; and place the guest page table into one of a plurality of restricted accessibility states based on the verification, the restricted accessibility applied to the VM guests and to the page walk processor.
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公开(公告)号：US09442868B2
公开(公告)日：2016-09-13
申请号：US14565718
申请日：2014-12-10
Applicant: Intel Corporation
Inventor： Gilbert Neiger , Rajesh Sankaran Madukkarumukumana , Richard A. Uhlig , Udo Steinberg , Sebastian Schoenberg , Sridhar Muthrasanallur , Steven M. Bennett , Andrew V. Anderson , Erik C. Cota-Robles
CPC classification number: G06F13/24 , G06F9/45533 , G06F9/4812
Abstract: Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.
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公开(公告)号：US09372807B2
公开(公告)日：2016-06-21
申请号：US14867027
申请日：2015-09-28
Applicant: Intel Corporation
Inventor： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard Uhlig , Scott Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
CPC classification number: G06F12/1027 , G06F9/3004 , G06F9/30076 , G06F9/45558 , G06F12/0246 , G06F12/0875 , G06F12/1009 , G06F12/1036 , G06F12/1054 , G06F2009/45583 , G06F2212/152 , G06F2212/2022 , G06F2212/452 , G06F2212/50 , G06F2212/65 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/7201
Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
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Patent Agency Ranking
公开(公告)号：US09372806B2
公开(公告)日：2016-06-21
申请号：US14867024
申请日：2015-09-28
Applicant: Intel Corporation
Inventor： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard A Uhlig , Scott Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
CPC classification number: G06F12/1027 , G06F9/3004 , G06F9/30076 , G06F9/45558 , G06F12/0246 , G06F12/0875 , G06F12/1009 , G06F12/1036 , G06F12/1054 , G06F2009/45583 , G06F2212/152 , G06F2212/2022 , G06F2212/452 , G06F2212/50 , G06F2212/65 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/7201
Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
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公开(公告)号：US09330021B2
公开(公告)日：2016-05-03
申请号：US14867020
申请日：2015-09-28
Applicant: Intel Corporation
Inventor： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard A Uhlig , Scott Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
CPC classification number: G06F12/1027 , G06F9/3004 , G06F9/30076 , G06F9/45558 , G06F12/0246 , G06F12/0875 , G06F12/1009 , G06F12/1036 , G06F12/1054 , G06F2009/45583 , G06F2212/152 , G06F2212/2022 , G06F2212/452 , G06F2212/50 , G06F2212/65 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/7201
Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
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公开(公告)号：US09244712B2
公开(公告)日：2016-01-26
申请号：US14060947
申请日：2013-10-23
Applicant: Intel Corporation
Inventor： Erik C. Cola-Robles , Gilbert Neiger , Steven M. Bennett , Andrew V. Anderson
CPC classification number: G06F9/45533 , G06F9/455 , G06F9/45558 , G06F9/46 , G06F9/461 , G06F9/462 , G06F9/468 , G06F11/3409 , G06F11/3466 , G06F11/348 , G06F2009/45591 , G06F2201/815 , G06F2201/86 , G06F2201/88 , G06F2201/885
Abstract: Embodiments of apparatuses, methods, and systems for virtualizing performance counters are disclosed. In one embodiment, an apparatus includes a counter, a counter enable storage location, counter enable logic, and virtual machine control logic. The counter enable storage location is to store a counter enable indicator. The counter enable logic is to enable the counter based on the counter enable indicator. The virtual machine control logic is to transfer control of the apparatus to a guest. The virtual machine control logic includes guest state load logic to cause a guest value from a virtual machine control structure to be loaded into the counter enable storage location in connection with a transfer of control of the apparatus to the guest.
Abstract translation: 公开了用于虚拟化性能计数器的装置，方法和系统的实施例。 在一个实施例中，装置包括计数器，计数器使能存储位置，计数器使能逻辑和虚拟机器控制逻辑。 计数器使能存储位置是存储计数器使能指示符。 计数器使能逻辑是基于计数器使能指示器启用计数器。 虚拟机控制逻辑是将设备的控制传送给客人。 虚拟机控制逻辑包括客户端状态负载逻辑，以使来自虚拟机控制结构的客户值被加载到计数器使能存储位置中，并将该设备的控制转移给客户端。
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公开(公告)号：US20160019163A1
公开(公告)日：2016-01-21
申请号：US14867025
申请日：2015-09-28
Applicant: Intel Corporation
Inventor： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard A. Uhlig , Scott Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
CPC classification number: G06F12/1027 , G06F9/3004 , G06F9/30076 , G06F9/45558 , G06F12/0246 , G06F12/0875 , G06F12/1009 , G06F12/1036 , G06F12/1054 , G06F2009/45583 , G06F2212/152 , G06F2212/2022 , G06F2212/452 , G06F2212/50 , G06F2212/65 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/7201
Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
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公开(公告)号：US09141555B2
公开(公告)日：2015-09-22
申请号：US14675297
申请日：2015-03-31
Applicant: Intel Corporation
Inventor： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard Uhlig , Scott Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
IPC: G06F12/10
CPC classification number: G06F12/1027 , G06F9/3004 , G06F9/30076 , G06F9/45558 , G06F12/0246 , G06F12/0875 , G06F12/1009 , G06F12/1036 , G06F12/1054 , G06F2009/45583 , G06F2212/152 , G06F2212/2022 , G06F2212/452 , G06F2212/50 , G06F2212/65 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/7201
Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
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