公开(公告)号：US11074151B2

公开(公告)日：2021-07-27

申请号：US15940966

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Bruce Querbach ,  Christopher Connor

IPC: G06F11/34 ,  G06F11/00 ,  G06F11/30 ,  G06F11/14

Abstract: A method is described. The method includes monitoring reliability, power consumption and performance of a processor and writing reliability, power consumption and performance data of the processor into an embedded non-volatile random access memory that is integrated into the processor's semiconductor chip.

公开(公告)号：US10242717B2

公开(公告)日：2019-03-26

申请号：US15808390

申请日：2017-11-09

Applicant: INTEL CORPORATION

Inventor： Bruce Querbach ,  Pete D. Vogt

IPC: G11C8/00 ,  G11C5/06 ,  G06F1/18 ,  H01R12/71 ,  H05K1/18 ,  G11C5/04 ,  H05K1/14 ,  H05K1/02

Abstract: Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board that includes a first row of elements including a first CPU positioned between first and second groups of dual in-line memory modules (DIMMs). The printed circuit board also includes a second row of elements including a second CPU positioned between third and fourth groups of DIMMs. The apparatus also includes a third row of elements including a fifth group of DIMMs, wherein the second row of elements is positioned between the first row of elements and the third row of elements. Other embodiments are described and claimed.

公开(公告)号：US10163508B2

公开(公告)日：2018-12-25

申请号：US15055153

申请日：2016-02-26

Applicant: Intel Corporation

Inventor： Woojong Han ,  Mohamed Arafa ,  Brian S. Morris ,  Mani Prakash ,  James K. Pickett ,  John K. Grooms ,  Bruce Querbach ,  Edward L Payton ,  Dong Wang

IPC: G11C5/06 ,  G11C14/00 ,  G11C5/02 ,  G11C5/14

Abstract: Methods and apparatus related to supporting both DDR (Double Data Rate) and NVM (Non-Volatile Memory) DIMM (Dual Inline Memory Module) on the same memory slot are described. In one embodiment, a DIMM comprises volatile memory and non-volatile memory, and data is communicated with the volatile memory and the non-volatile memory via a single memory slot. Other embodiments are also disclosed and claimed.

公开(公告)号：US10163502B2

公开(公告)日：2018-12-25

申请号：US15396251

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： Christopher F. Connor ,  Bruce Querbach ,  Hanmant P. Belgal

IPC: G06F3/06 ,  G11C13/00

Abstract: In one embodiment, a non-volatile memory is controlled in a selectable read mode in response to commands from a processor. Selectable read modes may include a default read memory mode, for example, and a performance read memory mode having a shorter read pulse and a reduced read latency than the default read memory mode, for example. In one embodiment, the performance read memory mode may also have refresh operations at an increased frequency compared to that of the default read mode. Other aspects and advantages are described.

公开(公告)号：US20180143242A1

公开(公告)日：2018-05-24

申请号：US15360899

申请日：2016-11-23

Applicant: Intel Corporation

Inventor： Christopher F. Connor ,  Bruce Querbach ,  Gordon McFadden ,  Rahul Khanna

IPC: G01R31/28 ,  G06F17/50

CPC classification number: G01R31/2851 ,  G01R31/2855 ,  G06F17/5036

Abstract: Embodiments detailed herein include an apparatus that includes a reliability assessment engine (RAE) stored in non-volatile memory and processing circuitry to execute the RAE to: receive data of at least one physical condition from a plurality of intra-die variation monitoring circuits, apply the received data least one to at least one reliability physics model, and calculate at least one of an estimated amount of lifetime consumed and an estimated amount of lifetime remaining.

公开(公告)号：US09953694B2

公开(公告)日：2018-04-24

申请号：US15174946

申请日：2016-06-06

Applicant: Intel Corporation

Inventor： Bruce Querbach ,  Kuljit S. Bains ,  John B. Halbert

IPC: G11C7/00 ,  G11C11/406 ,  G06F3/06 ,  G11C14/00

CPC classification number: G11C11/40618 ,  G06F3/0604 ,  G06F3/0632 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/40622 ,  G11C14/0009

Abstract: A memory subsystem enables a refresh abort command. A memory controller can issue an abort for an in-process refresh command sent to a memory device. The refresh abort enables the memory controller to more precisely control the timing of operations executed by memory devices in the case where a refresh command causes refresh of multiple rows of memory. The memory controller can issue a refresh command during active operation of the memory device, which is active operation refresh as opposed to self-refresh when the memory device controls refreshing. The memory controller can then issue a refresh abort during the refresh, and prior to completion of the refresh. The memory controller thus has deterministic control over both the start of refresh as well as when the memory device can be made available for access.

公开(公告)号：US09824743B2

公开(公告)日：2017-11-21

申请号：US15585678

申请日：2017-05-03

Applicant: Intel Corporation

Inventor： Bruce Querbach ,  Kuljit Bains ,  John Halbert

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4094

CPC classification number: G11C11/40618 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4096

Abstract: Embodiments are generally directed to memory refresh operation with page open. An embodiment of a memory device includes a memory array including a plurality of memory banks; and a control logic to provide control operations for the memory device including a page open refresh mode, wherein the control logic is to perform a refresh cycle in response to a refresh command with a memory page of the memory array open, the refresh operation including precharge of one or more memory banks of the plurality of memory banks, refresh of the one or more memory banks, and activation of the memory page.

公开(公告)号：US20170249991A1

公开(公告)日：2017-08-31

申请号：US15055153

申请日：2016-02-26

Applicant: Intel Corporation

Inventor： Woojong Han ,  Mohamed Arafa ,  Brian S. Morris ,  Mani Prakash ,  James K. Pickett ,  John K. Grooms ,  Bruce Querbach ,  Edward L Payton ,  Dong Wang

IPC: G11C14/00 ,  G11C5/14 ,  G11C5/02

CPC classification number: G11C14/0009 ,  G11C5/02 ,  G11C5/025 ,  G11C5/141 ,  G11C11/005

Abstract: Methods and apparatus related to supporting both DDR (Double Data Rate) and NVM (Non-Volatile Memory) DIMM (Dual Inline Memory Module) on the same memory slot are described. In one embodiment, a DIMM comprises volatile memory and non-volatile memory, and data is communicated with the volatile memory and the non-volatile memory via a single memory slot. Other embodiments are also disclosed and claimed.

公开(公告)号：US09564245B2

公开(公告)日：2017-02-07

申请号：US14141239

申请日：2013-12-26

Applicant: INTEL CORPORATION

Inventor： Bruce Querbach ,  Theodore Z. Schoenborn ,  David J. Zimmerman ,  David G. Ellis ,  Christopher W. Hampson ,  Ifar Wan ,  Yulan Zhang ,  Ramakrishna Mallela ,  William K. Lui

IPC: G06F11/263 ,  G06F11/27 ,  G11C11/406 ,  G11C29/00 ,  G11C29/36 ,  G11C29/44 ,  G11C29/10

CPC classification number: G11C29/36 ,  G06F11/263 ,  G06F11/27 ,  G11C11/406 ,  G11C29/10 ,  G11C29/4401 ,  G11C29/72 ,  G11C29/78 ,  G11C2029/4402

Abstract: In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory.