公开(公告)号：US20200211927A1

公开(公告)日：2020-07-02

申请号：US16233808

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Cheng Xu ,  Yikang Deng ,  Junnan Zhao ,  Ying Wang ,  Chong Zhang ,  Kyu Oh Lee ,  Chandra Mohan Jha ,  Chia-Pin Chiu

IPC: H01L23/473 ,  H01L21/48

Abstract: Microelectronic assemblies that include a cooling channel, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface, a die having a surface, and a fluidic channel between the surface of the die and the surface of the package substrate, wherein a top surface of the fluidic channel is defined by the surface of the die and a bottom surface of the fluidic channel is defined by the surface of the package substrate. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a surface; and an interposer having a fluidic channel between the surface of the die and the surface of the package substrate.

公开(公告)号：US20250096178A1

公开(公告)日：2025-03-20

申请号：US18969889

申请日：2024-12-05

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Sergio Antonio Chan Arguedas ,  Jimin Yao ,  Chandra Mohan Jha

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/367

Abstract: Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.

公开(公告)号：US12191220B2

公开(公告)日：2025-01-07

申请号：US16659395

申请日：2019-10-21

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Chandra Mohan Jha ,  Je-Young Chang ,  Chia-Pin Chiu

IPC: H01L23/15 ,  H01L23/00 ,  H01L23/373 ,  H01L23/498 ,  H01L25/18

Abstract: Embodiments include semiconductor packages. A semiconductor package includes a hybrid interposer with a first region and a second region. The first region is comprised of glass or low thermal conductive materials, and the second region is comprised of silicon or diamond materials. The semiconductor package includes a first die on the first region of the hybrid interposer, a second die on the second region of the hybrid interposer, and an integrated heat spreader over the first die, the second die, and the hybrid interposer. The hybrid interposer includes first and second interconnects, where the first interconnects vertically extend from a bottom surface of the first region to a top surface of the first region, and where the second interconnects vertically extend from a bottom surface of the second region to a top surface of the second region. The first interconnects are through-glass vias, and the second interconnects are through-silicon vias.

公开(公告)号：US11837519B2

公开(公告)日：2023-12-05

申请号：US16783819

申请日：2020-02-06

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Chia-Pin Chiu ,  Chandra Mohan Jha

IPC: H01L23/15 ,  H01L23/367 ,  H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/367 ,  H01L23/5386 ,  H01L25/0652 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/16 ,  H01L2224/16221

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises an interposer, a first die attached to the interposer, and a second die attached to the interposer. In an embodiment, the electronic package further comprises a heatsink thermally coupled to the first die and the second die. In an embodiment, the heatsink has a first surface facing away from the first die and the second die and a second surface facing the first die and the second die. In an embodiment, the heatsink comprises a thermal break between the first die and the second die.

公开(公告)号：US11756860B2

公开(公告)日：2023-09-12

申请号：US16522443

申请日：2019-07-25

Applicant: Intel Corporation

Inventor： Shrenik Kothari ,  Chandra Mohan Jha ,  Weihua Tang ,  Robert Sankman ,  Xavier Brun ,  Pooya Tadayon

IPC: H01L23/42 ,  H01L23/522 ,  H01L23/373 ,  H01L23/367 ,  H01L25/07 ,  H01L23/538

CPC classification number: H01L23/42 ,  H01L23/367 ,  H01L23/3738 ,  H01L23/522 ,  H01L23/5384 ,  H01L25/072

Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

公开(公告)号：US11735552B2

公开(公告)日：2023-08-22

申请号：US16451754

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Sergio Antonio Chan Arguedas ,  Jimin Yao ,  Chandra Mohan Jha

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/367

CPC classification number: H01L24/17 ,  H01L23/16 ,  H01L23/3675 ,  H01L23/562 ,  H01L2224/1713 ,  H01L2224/17051 ,  H01L2224/17163 ,  H01L2224/17181 ,  H01L2224/17519

Abstract: Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.

公开(公告)号：US11694942B2

公开(公告)日：2023-07-04

申请号：US16168534

申请日：2018-10-23

Applicant: Intel Corporation

Inventor： Kelly Lofgreen ,  Chandra Mohan Jha ,  Krishna Vasanth Valavala

IPC: H01L23/38 ,  H10N10/01 ,  H10N10/17 ,  H10N10/851 ,  H10N19/00 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48 ,  H01L25/16

CPC classification number: H01L23/38 ,  H10N10/01 ,  H10N10/17 ,  H10N10/851 ,  H10N19/101 ,  H01L23/481 ,  H01L24/09 ,  H01L25/165 ,  H01L25/50 ,  H01L2924/1432 ,  H01L2924/1434

Abstract: An integrated circuit (IC) package comprising an IC die, the IC die having a first surface and an opposing second surface. The IC die comprises a semiconductor material. The first surface comprises an active layer. A thermoelectric cooler (TEC) comprising a thermoelectric material is embedded within the IC die between the first surface and the second surface and adjacent to the active layer. The TEC has an annular shape that is substantially parallel to the first and second surfaces of the IC die. The thermoelectric material is confined between an outer sidewall along an outer perimeter of the TEC and an inner sidewall along an inner perimeter of the TEC. The outer and inner sidewalls are substantially orthogonal to the first and second surfaces of the IC die.

公开(公告)号：US11664293B2

公开(公告)日：2023-05-30

申请号：US16665621

申请日：2019-10-28

Applicant: Intel Corporation

Inventor： Krishna Vasanth Valavala ,  Ravindranath V. Mahajan ,  Chandra Mohan Jha

IPC: H01L23/38 ,  H01L23/42 ,  H01L23/367 ,  H01L23/10 ,  H01L21/48 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/38 ,  H01L21/4871 ,  H01L23/10 ,  H01L23/367 ,  H01L23/42 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16225

Abstract: Embodiments include a semiconductor package with a thermoelectric cooler (TEC), a method to form such semiconductor package, and a semiconductor packaged system. The semiconductor package includes a die with a plurality of backend layers on a package substrate. The backend layers couple the die to the package substrate. The semiconductor package includes the TEC in the backend layers of the die. The TEC includes a plurality of N-type layers, a plurality of P-type layers, and first and second conductive layers. The first conductive layer is directly coupled to outer regions of bottom surfaces of the N-type and P-type layers, and the second conductive layer is directly coupled to inner regions of top surfaces of the N-type and P-type layers. The first conductive layer has a width greater than a width of the second conductive layer. The N-type and P-type layers are directly disposed between the first and second conductive layers.

公开(公告)号：US20230081139A1

公开(公告)日：2023-03-16

申请号：US17475726

申请日：2021-09-15

Applicant: Intel Corporation

Inventor： Krishna Vasanth Valavala ,  Chandra Mohan Jha ,  Andrew Paul Collins ,  Omkar G. Karhade

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L23/367 ,  H01L25/00

Abstract: An example microelectronic assembly includes a substrate, a bridge die over the substrate, and a die stack between the substrate and the bridge die, the die stack including a logic die and at least one memory die, where the logic die is between the at least one memory die and the bridge die.