公开(公告)号：US12074138B2

公开(公告)日：2024-08-27

申请号：US18378978

申请日：2023-10-11

Applicant: Intel Corporation

Inventor： Mark T. Bohr ,  Wilfred Gomes ,  Rajesh Kumar ,  Pooya Tadayon ,  Doug Ingerly

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/13 ,  H01L2225/06541

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

公开(公告)号：US12032002B2

公开(公告)日：2024-07-09

申请号：US17677847

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Pooya Tadayon

IPC: G01R1/067 ,  G01R1/073 ,  G01R31/28

CPC classification number: G01R1/0675 ,  G01R1/06716 ,  G01R1/07314 ,  G01R1/07357 ,  G01R31/2889

Abstract: An apparatus an apparatus comprising: a substrate having a plane; and an array of at least one conductive probe having a base affixed to the substrate, the at least one conductive probe having a major axis extending from the plane of the substrate and terminating at a tip, wherein the one or more conductive probes comprise at least three points that are non-collinear.

公开(公告)号：US11817423B2

公开(公告)日：2023-11-14

申请号：US16524743

申请日：2019-07-29

Applicant: Intel Corporation

Inventor： Pooya Tadayon

IPC: H01L25/065 ,  H01L23/13 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0652 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06589

Abstract: Embodiments include a package substrate and semiconductor packages. A package substrate includes a first cavity in a top surface, first conductive pads on a first surface of the first cavity, a second cavity in a bottom surface, second conductive pads on a second surface of the second cavity, where the first surface is above the second surface, and a third cavity in the first and second cavities, where the third cavity vertically extends from the top surface to the bottom surface. The third cavity overlaps a first portion of the first cavity and a second portion of the second cavity. The package substrate may include conductive lines coupled to the first and second conductive pads, a first die in the first cavity, a second die in the second cavity, and interconnects in the third cavity that directly couple first die to the second die.

公开(公告)号：US20230197622A1

公开(公告)日：2023-06-22

申请号：US17559431

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Karumbu Meyyappan ,  Jeffory L, Smalley ,  Gregorio Murtagian ,  Srikant Nekkanty ,  Pooya Tadayon ,  Eric J.M. Moret ,  Bijoyraj Sahu

IPC: H01L23/538 ,  H01L23/498 ,  H01R12/52 ,  H01L25/00 ,  H01L25/18 ,  H01L25/065 ,  H01R12/58 ,  H05K3/32 ,  H05K1/18

CPC classification number: H01L23/5384 ,  H01L23/49827 ,  H01L23/5385 ,  H01R12/52 ,  H01L25/50 ,  H01L25/18 ,  H01L25/0655 ,  H01R12/58 ,  H05K3/32 ,  H05K1/181 ,  H05K2201/10189 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/1053

Abstract: An electronic system and associated methods are disclosed. In one example, the electronic system includes an interposer including electrically conductive interposer interconnect, a first interposer surface, and a second interposer surface; a processor package including at least one processor integrated circuit (IC), the processor package attached to the first interposer surface and electrically connected to the interposer interconnect; a first liquid metal well array including multiple liquid metal wells attached to a second interposer surface and the interposer interconnect; a second liquid metal well array including a first array surface attached to the first interposer surface and the interposer interconnect; and a packaged companion IC to the processor IC attached to a second array surface of the second liquid metal well array.

公开(公告)号：US20230187850A1

公开(公告)日：2023-06-15

申请号：US17549427

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Ziyin Lin ,  Aaron Michael Garelick ,  Karumbu Meyyappan ,  Gregorio Murtagian ,  Srikant Nekkanty ,  Taylor Rawlings ,  Jeffory L. Smalley ,  Pooya Tadayon ,  Dingying Xu

IPC: H01R3/08 ,  H01L23/498 ,  H01L23/32 ,  H01R43/00

CPC classification number: H01R3/08 ,  H01L23/49816 ,  H01L23/32 ,  H01L23/49833 ,  H01R43/005

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a socket that includes one or more liquid metal filled reservoirs. In selected examples, the electronic devices and sockets include configurations to aid in reducing ingress of moisture.

公开(公告)号：US20230095039A1

公开(公告)日：2023-03-30

申请号：US17478337

申请日：2021-09-17

Applicant: Intel Corporation

Inventor： Srikant Nekkanty ,  Pooya Tadayon ,  Xavier F. Brun ,  Wesley B. Morgan ,  John M. Heck ,  Joseph F. Walczyk ,  Paul J. Diglio

IPC: G02B6/26

Abstract: Technologies for optical coupling to photonic integrated circuit (PIC) dies are disclosed. In the illustrative embodiment, a lens assembly with one or more lenses is positioned to collimate light coming out of one or more waveguides in the PIC die. Part of the illustrative lens assembly extends above a top surface of the PIC die and is in contact with the PIC die. The top surface of the PIC die establishes the vertical positioning of the lens assembly. In the illustrative embodiment, the lens assembly is positioned at least partially inside a cavity defined within the PIC die, which allows the lens assembly to be integrated at the wafer level, before singulation into individual dies.

公开(公告)号：US11249113B2

公开(公告)日：2022-02-15

申请号：US17111298

申请日：2020-12-03

Applicant: Intel Corporation

Inventor： Pooya Tadayon ,  Mark Bohr ,  Joe Walczyk

IPC: G01R1/073 ,  H01L23/48 ,  H01L23/32 ,  H01L21/48 ,  H01L21/027 ,  G01R31/28 ,  H01L23/14

Abstract: An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.

公开(公告)号：US20210375716A1

公开(公告)日：2021-12-02

申请号：US16889562

申请日：2020-06-01

Applicant: INTEL CORPORATION

Inventor： Pooya Tadayon ,  Joe Walczyk

IPC: H01L23/373

Abstract: A hybrid thermal interface material (TIM) suitable for an integrated circuit (IC) die package assembly. The hybrid TIM may include a heat-spreading material having a high planar thermal conductivity, and a supplemental material having a high perpendicular thermal conductivity at least partially filling through-holes within the heat-spreading material. The hybrid TIM may offer a reduced effective spreading and vertical thermal resistance. The heat-spreading material may have high compressibility (low bulk modulus or low hardness), such as a carbon-based (e.g., graphitic) material. The supplemental material may be of a suitable composition for filling the through-hole. The heat-spreading material, once compressed by a force applied through an IC die package assembly, may have a thickness substantially the same as that of the supplemental material such that both materials make contact with the IC die package and a thermal solution.

公开(公告)号：US11189585B2

公开(公告)日：2021-11-30

申请号：US16703298

申请日：2019-12-04

Applicant: Intel Corporation

Inventor： Brennen K. Mueller ,  Adel Elsherbini ,  Mauro Kobrinsky ,  Johanna Swan ,  Shawna Liff ,  Pooya Tadayon

IPC: H01L23/52 ,  H01L23/00

Abstract: An Integrated Circuit (IC) device comprising a first component, the first component comprising a first dielectric and a plurality of adjacent first interconnect structures within the first dielectric. The IC device comprising a second component, the second component comprising a second dielectric and a plurality of adjacent second interconnect structures within the second dielectric. A first of the second interconnect structures is in direct contact with a first of the first interconnect structures at a bond interface between the first and second components. A second of the first interconnect structures is set back a distance from a plane of the bond interface.

公开(公告)号：US11061068B2

公开(公告)日：2021-07-13

申请号：US15832650

申请日：2017-12-05

Applicant: Intel Corporation

Inventor： Pooya Tadayon ,  Justin Huttula

IPC: G01R31/28 ,  G01R3/00 ,  G01R1/067

Abstract: A testing arrangement for testing Integrated Circuit (IC) interconnects is provided. In an example, the testing arrangement includes a substrate, and a first interconnect structure. The first interconnect structure may include a first member having a first end to attach to the substrate and a second end opposite the first end, and a second member having a first end to attach to the substrate and a second end opposite the first end. In some examples, the second end of the first member and the second end of the second member are to contact a second interconnect structure of a IC device under test, and the first end of the first member and the first end of the second member are coupled such that the first member and the second member are to transmit, in parallel, current to the second interconnect structure of the IC device under test.