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    TRANSISTOR GATE STACKS WITH THICK HYSTERETIC ELEMENTS
    22.
    发明公开
    TRANSISTOR GATE STACKS WITH THICK HYSTERETIC ELEMENTS 审中-公开

    公开(公告)号：US20230307541A1

    公开(公告)日：2023-09-28

    申请号：US17702593

    申请日：2022-03-23

    Applicant: Intel Corporation

    Inventor： Abhishek A. Sharma ,  Wilfred Gomes ,  Tahir Ghani ,  Anand S. Murthy ,  Pushkar Sharad Ranade ,  Sagar Suthram

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

    CPC classification number: H01L29/78391 ,  H01L29/42364 ,  H01L29/516 ,  H01L29/6684

    Abstract: Disclosed herein are transistor gate-channel arrangements with transistor gate stacks that include thick hysteretic elements (i.e., hysteretic elements having a thickness of at least 10-15 nanometers, e.g., between 55 and 100 nanometers), and related methods and devices. Transistor gate stacks disclosed herein include a multilayer gate insulator having a thick hysteretic element and an interface layer, where the thick hysteretic element is between the interface layer and a gate electrode material, and the interface layer is between the thick hysteretic element and a channel material of a transistor. The interface layer may be a dielectric material with an effective dielectric constant of at least 20 and/or be a dielectric material that is thinner than about 3 nanometers. Such an interface layer may help improve gate control and allow use of thick hysteretic elements while maintaining transistor performance in terms of, e.g., gate leakage, carrier mobility, and subthreshold swing.

    MEMORY LAYERS BONDED TO LOGIC LAYERS WITH INCLINATION
    23.
    发明申请
    MEMORY LAYERS BONDED TO LOGIC LAYERS WITH INCLINATION 有权

    公开(公告)号：US20250107108A1

    公开(公告)日：2025-03-27

    申请号：US18473421

    申请日：2023-09-25

    Applicant: Intel Corporation

    Inventor： Abhishek A. Sharma ,  Sagar Suthram ,  Wilfred Gomes ,  Tahir Ghani ,  Anand S. Murthy ,  Pushkar Sharad Ranade

    IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

    Abstract: An IC device may include memory layers bonded to a logic layer with inclination. An angle between a memory layer and the logic layer may be in a range from approximately 0 to approximately 90 degrees. The memory layers may be over the logic layer. The IC device may include one or more additional logic layers that are parallel to a memory layer or perpendicular to a memory layer. The one or more additional logic layers may be over the logic layer. A memory layer may include memory cells. The logic layer may include logic circuits (e.g., sense amplifier, word line driver, etc.) that control the memory cells. Bit lines (or word lines) in different memory layers may be coupled to each other. A bit line and a word line in a memory layer may be controlled by logic circuits in different logic layers.

    STACKED MEMORY LAYERS WITH UNIFORM ACCESS
    24.
    发明申请
    STACKED MEMORY LAYERS WITH UNIFORM ACCESS 有权

    公开(公告)号：US20250107107A1

    公开(公告)日：2025-03-27

    申请号：US18471402

    申请日：2023-09-21

    Applicant: Intel Corporation

    Inventor： Abhishek A. Sharma ,  Sagar Suthram ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Anand S. Murthy ,  Tahir Ghani

    IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

    Abstract: An IC device may include memory layers over a logic layer. A memory layer may include memory arrays and one or more peripheral circuits coupled to the memory arrays. A memory array may include memory cells arranged in rows and columns. A row of memory cells may be associated with a word line. A column of memory cells may be associated with a bit line. The logic layer includes one or more logic circuits that can control data read operations and data write operations of the memory layers. The logic layer may also include a power interconnect, which facilitates power delivery to the memory layers, and a signal interconnect, which facilitates signal transmission within the IC device. The IC device may further include vias that couple the memory layers to the logic layer. Each via may be connected to one or more memory layers and the logic layer.

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