公开(公告)号：US20190042160A1

公开(公告)日：2019-02-07

申请号：US16147024

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Raghavan KUMAR ,  Phil KNAG ,  Gregory K. CHEN ,  Huseyin Ekin SUMBUL ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Ram KRISHNAMURTHY ,  Ian A. YOUNG

IPC: G06F3/06 ,  G04F10/00 ,  G11C11/419 ,  G11C13/00 ,  G11C11/418

Abstract: A memory circuit has compute-in-memory (CIM) circuitry that performs computations based on time-to-digital conversion (TDC). The memory circuit includes an array of memory cells addressable with column address and row address. The memory circuit includes CIM sense circuitry to sense a voltage for multiple memory cells triggered together. The CIM sense circuitry including a TDC circuit to convert a time for discharge of the multiple memory cells to a digital value. A processing circuit determines a value of the multiple memory cells based on the digital value.

公开(公告)号：US20180145691A1

公开(公告)日：2018-05-24

申请号：US15567945

申请日：2015-05-28

Applicant: Intel Corporation

Inventor： Sasikanth MANIPATRUNI ,  Dmitri NIKONOV ,  Ian A. Young

IPC: H03K19/21 ,  H01L43/08 ,  H03K19/18 ,  H01L43/04

CPC classification number: H03K19/21 ,  H01L43/04 ,  H01L43/08 ,  H03K19/18

Abstract: Described is an apparatus which comprises: a first layer formed of a material that exhibits spin orbit torque effect; a second layer formed of material that exhibits spin orbit torque effect; and a magnetic tunneling junction (MTJ) including first and second free magnetic layers, wherein the first free magnetic layer is coupled to the first layer and wherein the second free magnetic layer is coupled to the second layer.

公开(公告)号：US20170148903A1

公开(公告)日：2017-05-25

申请号：US15427968

申请日：2017-02-08

Applicant: Intel Corporation

Inventor： Sasikanth MANIPATRUNI ,  Dmitri E. NIKONOV ,  Ian A. YOUNG

IPC: H01L29/66 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16 ,  H01L43/08

CPC classification number: H01L29/66984 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1697 ,  H01L27/226 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H03K19/16

Abstract: Described is an apparatus, for spin state element device, which comprises: a variable resistive magnetic (VRM) device to receive a magnetic control signal to adjust resistance of the VRM device; and a magnetic logic gating (MLG) device, coupled to the VRM device, to receive a magnetic logic input and perform logic operation on the magnetic logic input and to drive an output magnetic signal based on the resistance of the VRM device. Described is a magnetic de-multiplexer which comprises: a first VRM device to receive a magnetic control signal to adjust resistance of the first VRM; a second VRM device to receive the magnetic control signal to adjust resistance of the second VRM device; and an MLG device, coupled to the first and second VRM devices, the MLG device having at least two output magnets to output magnetic signals based on the resistances of the first and second VRM devices.

公开(公告)号：US20150228323A1

公开(公告)日：2015-08-13

申请号：US14696965

申请日：2015-04-27

Applicant: Intel Corporation

Inventor： Sasikanth MANIPATRUNI ,  Dmitri E. NIKONOV ,  Ian A. YOUNG

IPC: G11C11/16

CPC classification number: H01L29/66984 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1697 ,  H01L27/226 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H03K19/16

Abstract: Described is an apparatus, for spin state element device, which comprises: a variable resistive magnetic (VRM) device to receive a magnetic control signal to adjust resistance of the VRM device; and a magnetic logic gating (MLG) device, coupled to the VRM device, to receive a magnetic logic input and perform logic operation on the magnetic logic input and to drive an output magnetic signal based on the resistance of the VRM device. Described is a magnetic de-multiplexer which comprises: a first VRM device to receive a magnetic control signal to adjust resistance of the first VRM; a second VRM device to receive the magnetic control signal to adjust resistance of the second VRM device; and an MLG device, coupled to the first and second VRM devices, the MLG device having at least two output magnets to output magnetic signals based on the resistances of the first and second VRM devices.

Abstract translation: 描述了一种用于自旋状态元件器件的装置，其包括：可变电阻磁极（VRM）器件，用于接收磁控制信号以调节VRM器件的电阻; 以及耦合到VRM装置的磁逻辑门控（MLG）装置，以接收磁逻辑输入并对磁逻辑输入执行逻辑运算，并且基于VRM装置的电阻来驱动输出磁信号。 描述的磁解除多路复用器包括：第一VRM装置，用于接收磁控制信号以调整第一VRM的电阻; 第二VRM装置，用于接收所述磁控信号以调整所述第二VRM装置的电阻; 以及耦合到第一和第二VRM装置的MLG装置，MLG装置具有至少两个输出磁体，以基于第一和第二VRM装置的电阻输出磁信号。

公开(公告)号：US20220140230A1

公开(公告)日：2022-05-05

申请号：US17578093

申请日：2022-01-18

Applicant: Intel Corporation

Inventor： Sasikanth MANIPATRUNI ,  Kaan OGUZ ,  Chia-Ching LIN ,  Christopher WIEGAND ,  Tanay GOSAVI ,  Ian YOUNG

IPC: H01L43/02 ,  H01F10/32 ,  G11C11/16 ,  H01L43/10 ,  H01L27/22

Abstract: An apparatus is provided which comprises: a magnetic junction including: a stack of structures including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device, wherein the first structure has a first dimension along the x-y plane and a second dimension in the z-plane, wherein the second dimension is substantially greater than the first dimension. The magnetic junction includes a second structure comprising one of a dielectric or metal; and a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; and an interconnect adjacent to the third structure, wherein the interconnect comprises a spin orbit material.

公开(公告)号：US20200233923A1

公开(公告)日：2020-07-23

申请号：US16839013

申请日：2020-04-02

Applicant: Intel Corporation

Inventor： Phil KNAG ,  Gregory K. CHEN ,  Raghavan KUMAR ,  Huseyin Ekin SUMBUL ,  Abhishek SHARMA ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Ram KRISHNAMURTHY ,  Ian A. YOUNG

IPC: G06F17/16 ,  G06N3/063 ,  G11C8/08 ,  G11C7/12 ,  G11C7/10 ,  G06F9/30 ,  G11C11/56 ,  G11C11/418 ,  G11C11/419

Abstract: A binary CIM circuit enables all memory cells in a memory array to be effectively accessible simultaneously for computation using fixed pulse widths on the wordlines and equal capacitance on the bitlines. The fixed pulse widths and equal capacitance ensure that a minimum voltage drop in the bitline represents one least significant bit (LSB) so that the bitline voltage swing remains safely within the maximum allowable range. The binary CIM circuit maximizes the effective memory bandwidth of a memory array for a given maximum voltage range of bitline voltage.

公开(公告)号：US20200161535A1

公开(公告)日：2020-05-21

申请号：US16193599

申请日：2018-11-16

Applicant: Intel Corporation

Inventor： Chia-Ching LIN ,  Tanay GOSAVI ,  Sasikanth MANIPATRUNI ,  Dmitri NIKONOV ,  Ian YOUNG

IPC: H01L43/02 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16 ,  H01F10/32

Abstract: A memory apparatus is provided which comprises: a stack comprising a magnetic insulating material and a transition metal dichalcogenide (TMD), wherein the magnetic insulating material has a first magnetization. The stack behaves as a free magnet. The apparatus includes a fixed magnet with a second magnetization. An interconnect is further provided which comprises a spin orbit material, wherein the interconnect is adjacent to the stack.

公开(公告)号：US20200098826A1

公开(公告)日：2020-03-26

申请号：US16141025

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Abhishek SHARMA ,  Gregory CHEN ,  Phil KNAG ,  Ram KRISHNAMURTHY ,  Raghavan KUMAR ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Huseyin SUMBUL ,  Ian A. YOUNG

IPC: H01L27/24 ,  H01L29/78 ,  H01L45/00 ,  H01L29/66

Abstract: Embodiments herein describe techniques for a semiconductor device including a RRAM memory cell. The RRAM memory cell includes a FinFET transistor and a RRAM storage cell. The FinFET transistor includes a fin structure on a substrate, where the fin structure includes a channel region, a source region, and a drain region. An epitaxial layer is around the source region or the drain region. A RRAM storage stack is wrapped around a surface of the epitaxial layer. The RRAM storage stack includes a resistive switching material layer in contact and wrapped around the surface of the epitaxial layer, and a contact electrode in contact and wrapped around a surface of the resistive switching material layer. The epitaxial layer, the resistive switching material layer, and the contact electrode form a RRAM storage cell. Other embodiments may be described and/or claimed.

公开(公告)号：US20200083427A1

公开(公告)日：2020-03-12

申请号：US16128426

申请日：2018-09-11

Applicant: Intel Corporation

Inventor： Sasikanth MANIPATRUNI ,  Kaan OGUZ ,  Chia-Ching LIN ,  Christopher WIEGAND ,  Tanay GOSAVI ,  Ian YOUNG

IPC: H01L43/02 ,  H01F10/32 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16

Abstract: An apparatus is provided which comprises: a magnetic junction including: a stack of structures including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device, wherein the first structure has a first dimension along the x-y plane and a second dimension in the z-plane, wherein the second dimension is substantially greater than the first dimension. The magnetic junction includes a second structure comprising one of a dielectric or metal; and a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; and an interconnect adjacent to the third structure, wherein the interconnect comprises a spin orbit material.

公开(公告)号：US20190259935A1

公开(公告)日：2019-08-22

申请号：US16346872

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Jasmeet S. CHAWLA ,  Sasikanth MANIPATRUNI ,  Robert L. BRISTOL ,  Chia-Ching LIN ,  Dmitri E. NIKONOV ,  Ian A. YOUNG

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: Magneto-electric spin orbital (MESO) structures having functional oxide vias, and method of fabricating magneto-electric spin orbital (MESO) structures having functional oxide vias, are described. In an example, a magneto-electric spin orbital (MESO) device includes a source region and a drain region in or above a substrate. A first via contact is on the source region. A second via contact is on the drain region, the second via contact laterally adjacent to the first via contact. A plurality of alternating ferromagnetic material lines and non-ferromagnetic conductive lines is above the first and second via contacts. A first of the ferromagnetic material lines is on the first via contact, and a second of the ferromagnetic material lines is on the second via contact. A spin orbit coupling (SOC) via is on the first of the ferromagnetic material lines. A functional oxide via is on the second of the ferromagnetic material lines.