公开(公告)号：US11469213B2

公开(公告)日：2022-10-11

申请号：US16325970

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Thomas Wagner ,  Klaus Reingruber ,  Bernd Waidhas ,  Andreas Wolter

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L29/06 ,  H01L23/31

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing reduced height semiconductor packages for mobile electronics. For instance, there is disclosed in accordance with one embodiment a stacked die package having therein a bottom functional silicon die; a recess formed within the bottom functional silicon die by a thinning etch partially reducing a vertical height of the bottom functional silicon die at the recess; and a top component positioned at least partially within the recess formed within the bottom functional silicon die. Other related embodiments are disclosed.

公开(公告)号：US11374323B2

公开(公告)日：2022-06-28

申请号：US16473566

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Andreas Augustin ,  Sonja Koller ,  Bernd Waidhas ,  Georg Seidemann ,  Andreas Wolter ,  Stephan Stoeckl ,  Thomas Wagner ,  Josef Hagn

IPC: H01Q9/04 ,  H01L23/00 ,  H01Q1/22 ,  H01Q21/06

Abstract: A patch antenna array is fabricated with a package-on-package setup that contains a transceiver. The patch antenna array has a footprint that intersects the transceiver footprint. The package-on-package setup includes through-mold vias that couple to a redistribution layer disposed between the patch antennas and the package-on-package setup.

公开(公告)号：US11211337B2

公开(公告)日：2021-12-28

申请号：US16703315

申请日：2019-12-04

Applicant: Intel Corporation

Inventor： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L25/16 ,  H01L25/00 ,  H01L23/498

Abstract: A face-up fan-out electronic package including at least one passive component located on a support. The electronic package can include a die. The die can include a plurality of conductive pillars having a proximal end communicatively coupled to the first side of the die and a distal end opposite the proximal end. A mold can at least partially surround the die. The mold can include a first surface that is coplanar with the distal end of the conductive pillars and a second surface opposing the first surface. In an example, the passive component can include a body and a lead. The passive component can be located within the mold. The lead can be coplanar with the first surface, and the body can be located at a distance from the second surface. The support can be located between the body and the second surface.

公开(公告)号：US10403602B2

公开(公告)日：2019-09-03

申请号：US15637935

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Andreas Augustin ,  Laurent Millou ,  Andreas Wolter ,  Reinhard Mahnkopf ,  Stephan Stoeckl ,  Thomas Wagner

IPC: H01L21/48 ,  H01L25/065 ,  H01L23/48 ,  G06F15/76 ,  H01L25/00

Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.

公开(公告)号：US20240429221A1

公开(公告)日：2024-12-26

申请号：US18339685

申请日：2023-06-22

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Thomas Wagner ,  Georg Seidemann ,  Nicolas Richaud ,  Manisha Dutta ,  Georgios Dogiamis ,  Harshit Dhakad ,  Michael Langenbuch

IPC: H01L25/18 ,  H01L23/31 ,  H01L25/00 ,  H01L27/01 ,  H01Q1/22 ,  H01Q9/04

Abstract: Glass layers and capacitors for use with integrated circuit packages are disclosed. An example integrated circuit (IC) package includes a semiconductor die, a glass layer, and a capacitor electrically coupled to the semiconductor die, at least one side of the capacitor enclosed by the glass layer, the capacitor positioned closer to the glass layer than the semiconductor die is to the glass layer.

公开(公告)号：US12125815B2

公开(公告)日：2024-10-22

申请号：US17131663

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Andreas Wolter ,  Georg Seidemann ,  Thomas Wagner

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L24/20 ,  H01L23/3157 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/13 ,  H01L2924/3511 ,  H01L2924/381

Abstract: Embodiments disclosed herein include electronic package and methods of forming such packages. In an embodiment, an electronic package comprises a mold layer and a first die embedded in the mold layer. In an embodiment, the first die comprises first pads at a first pitch and second pads at a second pitch. In an embodiment, the electronic package further comprises a second die embedded in the mold layer, where the second die comprises third pads at the first pitch and fourth pads at the second pitch. In an embodiment, a bridge die is embedded in the mold layer, and the bridge die electrically couples the second pads to the fourth pads.

公开(公告)号：US11955395B2

公开(公告)日：2024-04-09

申请号：US17855674

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Lizabeth Keser ,  Bernd Waidhas ,  Thomas Ort ,  Thomas Wagner

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L23/3114 ,  H01L21/568 ,  H01L23/5226 ,  H01L24/11 ,  H01L24/14 ,  H01L24/96 ,  H01L28/10 ,  H01L28/40 ,  H01L2224/02379 ,  H01L2924/19011

Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.

公开(公告)号：US20230411348A1

公开(公告)日：2023-12-21

申请号：US17842093

申请日：2022-06-16

Applicant: Intel Corporation

Inventor： Carlton Hanna ,  Bernd Waidhas ,  Thomas Wagner

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/29 ,  H01L23/538 ,  H01L23/48

CPC classification number: H01L25/0652 ,  H01L24/73 ,  H01L24/16 ,  H01L24/08 ,  H01L24/09 ,  H01L21/565 ,  H01L21/486 ,  H01L23/293 ,  H01L23/5381 ,  H01L23/5385 ,  H01L23/481 ,  H01L24/05 ,  H01L2924/37001 ,  H01L2924/3512 ,  H01L2924/3841 ,  H01L2924/381 ,  H01L2924/1434 ,  H01L2924/1431 ,  H01L24/13 ,  H01L2224/13147 ,  H01L23/49816

Abstract: Embodiments of a microelectronic assembly comprise a first integrated circuit (IC) die having first bond-pads on a first surface; an organic dielectric material in contact with the first surface; second bond-pads on a second surface of the organic dielectric material opposite to the first surface; through-dielectric vias (TDVs) in the dielectric material between the first bond-pads and the second bond-pads, wherein the TDVs are in direct contact with the first bond-pads and the second bond-pads; a second IC die embedded in the organic dielectric material and coupled to the first bond-pads by first interconnects; and a package substrate coupled to the second bond-pads by second interconnects.

公开(公告)号：US20230282615A1

公开(公告)日：2023-09-07

申请号：US17685871

申请日：2022-03-03

Applicant: Intel Corporation

Inventor： Thomas Wagner ,  Abdallah Bacha ,  Vishnu Prasad ,  Mohan Prashanth Javare Gowda ,  Bernd Waidhas ,  Sonja Koller ,  Eduardo De Mesa ,  Jan Proschwitz ,  Lizabeth Keser

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/15311

Abstract: A microelectronic assembly is provided, comprising: an interposer having a first side and a second side opposite to the first side; a plurality of integrated circuit (IC) dies in a plurality of layers on the first side of the interposer, the plurality of IC dies being encased by a dielectric material; a package substrate on the second side of the interposer; a plurality of conductive vias through the plurality of layers; and redistribution layers adjacent to the layers in the plurality of layers, at least some of the redistribution layers comprising conductive traces coupling the conductive vias to the IC dies.

公开(公告)号：US20230197599A1

公开(公告)日：2023-06-22

申请号：US17554112

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Harald Gossner ,  Wolfgang Molzer ,  Georg Seidemann ,  Michael Langenbuch ,  Martin Ostermayr ,  Joachim Singer ,  Thomas Wagner ,  Klaus Herold

IPC: H01L23/522 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/535 ,  H01L27/092

CPC classification number: H01L23/5226 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0924

Abstract: IC devices including BPRs with integrated decoupling capacitance are disclosed. An example IC device includes a first layer comprising a transistor and a support structure adjoining the first layer. The support structure includes BPRs, which are power rails buried in the support structure, and a decoupling capacitor based on the BPRs. The conductive cores of the BPRs are the electrodes of the decoupling capacitor. The dielectric barriers of the BPRs can be the dielectric of the decupling capacitor. The dielectric of the decupling capacitor may also include a dielectric element between the BPRs. Additionally or alternatively, the IC device includes another decoupling capacitor at the backside of the support structure. The other decoupling capacitor is coupled to the BPRs and can provide additional decoupling capacitance for stabilizing power supply facilitated by the BPRs.