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    Nonvolatile Memory Elements
    21.
    发明申请
    Nonvolatile Memory Elements 有权
    非易失性存储元件

    公开(公告)号：US20130059427A1

    公开(公告)日：2013-03-07

    申请号：US13656585

    申请日：2012-10-19

    Applicant: Intermolecular, Inc.

    Inventor： Sandra G. Malhotra ,  Sean Barstow ,  Tony P. Chiang ,  Pragati Kumar ,  Prashant B. Phatak ,  Sunil Shanker ,  Wen Wu

    IPC: H01L21/02

    CPC classification number: H01L45/1608 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641

    Abstract: Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.

    Abstract translation: 提供了基于电阻式开关存储元件层的非易失性存储元件。 非易失性存储元件可以具有电阻性开关金属氧化物层。 电阻式开关金属氧化物层可以具有一层或多层氧化物。 电阻式开关金属氧化物可以掺杂有增加其熔融温度并增强其热稳定性的掺杂剂。 可以形成层以增强非易失性存储元件的热稳定性。 用于非易失性存储元件的电极可以包含导电层和缓冲层。

    Methods For Depositing High-K Dielectrics
    22.
    发明申请
    Methods For Depositing High-K Dielectrics 有权
    沉积高K电介质的方法

    公开(公告)号：US20130056852A1

    公开(公告)日：2013-03-07

    申请号：US13668488

    申请日：2012-11-05

    Applicant: Intermolecular, Inc.

    Inventor： Imran Hashim ,  Edward L. Haywood ,  Sandra G. Malhotra ,  Xiangxin Rui ,  Sunil Shanker

    IPC: H01L29/92

    CPC classification number: H01L21/3141 ,  C23C16/02 ,  C23C16/405 ,  H01L21/02186 ,  H01L21/02271 ,  H01L21/02315 ,  H01L21/31604 ,  H01L28/91

    Abstract: Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact angle of a surface of the metal, and depositing a titanium oxide layer on the exposed metal using at least one of a chemical vapor deposition process and an atomic layer deposition process, wherein the titanium oxide layer comprises at least a portion rutile titanium oxide.

    Abstract translation: 描述了用于沉积高K电介质的方法，包括在衬底上沉积第一电极，其中第一电极选自铂和钌，对暴露的金属施加氧等离子体处理以减小接触角 并且使用化学气相沉积工艺和原子层沉积工艺中的至少一种在暴露的金属上沉积氧化钛层，其中所述氧化钛层包含至少一部分金红石型氧化钛。

    Methods for reproducible flash layer deposition
    23.
    发明授权
    Methods for reproducible flash layer deposition 有权
    可重复闪蒸层沉积的方法

    公开(公告)号：US09105646B2

    公开(公告)日：2015-08-11

    申请号：US13731548

    申请日：2012-12-31

    Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

    Inventor： Sandra G. Malhotra ,  Hiroyuki Ode ,  Xiangxin Rui

    IPC: H01L21/02 ,  H01L49/02

    CPC classification number: H01L28/56 ,  H01L28/65 ,  H01L28/75

    Abstract: A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a flash layer between the dielectric layer and the first electrode layer. A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capping layer between the dielectric layer and the second electrode layer. The flash layer and the capping layer can be formed using an atomic layer deposition (ALD) technique. The precursor materials used for forming the flash layer and the capping layer are selected such they include at least one metal-oxygen bond. Additionally, the precursor materials are selected to also include “bulky” ligands.

    Abstract translation: 一种降低DRAM金属 - 绝缘体 - 金属电容器中的漏电流的方法包括在电介质层和第一电极层之间形成闪电层。 降低DRAM金属 - 绝缘体 - 金属电容器中漏电流的方法包括在电介质层和第二电极层之间形成覆盖层。 闪光层和覆盖层可以使用原子层沉积（ALD）技术形成。 选择用于形成闪光层和覆盖层的前体材料，使得它们包括至少一种金属 - 氧键。 此外，前体材料被选择为也包括“体积大”的配体。

    Band gap improvement in DRAM capacitors
    24.
    发明授权
    Band gap improvement in DRAM capacitors 有权
    DRAM电容器带隙改善

    公开(公告)号：US08878269B2

    公开(公告)日：2014-11-04

    申请号：US13738831

    申请日：2013-01-10

    Applicant: Intermolecular, Inc.

    Inventor： Hanhong Chen ,  Wim Deweerd ,  Sandra G. Malhotra ,  Hiroyuki Ode

    IPC: H01L27/108

    CPC classification number: H01L28/40 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L27/1085 ,  H01L28/60

    Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of an compound high k dielectric material. The dielectric material further comprises a dopant. One component of the compound high k dielectric material is present in a concentration between about 30 atomic % and about 80 atomic and more preferably between about 40 atomic % and about 60 atomic %. In some embodiments, the compound high k dielectric material comprises an alloy of TiO2 and ZrO2 and further comprises a dopant of Al2O3. In some embodiments, the compound high k dielectric material comprises an admixture of TiO2 and HfO2 and further comprises a dopant of Al2O3.

    Abstract translation: 用于形成具有低漏电流和低EOT的DRAM MIM电容器堆叠的方法涉及使用复合高k电介质材料。 电介质材料还包括掺杂剂。 复合高k介电材料的一个组分以约30原子％至约80原子之间的浓度存在，更优选约40原子％至约60原子％之间。 在一些实施方案中，化合物高k介电材料包含TiO 2和ZrO 2的合金，并且还包含Al 2 O 3的掺杂剂。 在一些实施方案中，化合物高k介电材料包含TiO 2和HfO 2的混合物，并且还包含Al 2 O 3的掺杂剂。

    Blocking layers for leakage current reduction in DRAM devices
    26.
    发明授权
    Blocking layers for leakage current reduction in DRAM devices 有权

    公开(公告)号：US08569818B2

    公开(公告)日：2013-10-29

    申请号：US13658065

    申请日：2012-10-23

    Applicant: Intermolecular, Inc.

    Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Y. Deweerd ,  Hiroyuki Ode

    IPC: H01L29/94 ,  H01L21/20

    CPC classification number: H01L28/60 ,  H01L27/10852 ,  H01L28/40

    Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

    High performance dielectric stack for DRAM capacitor
    27.
    发明授权
    High performance dielectric stack for DRAM capacitor 有权
    用于DRAM电容器的高性能电介质堆叠

    公开(公告)号：US08546236B2

    公开(公告)日：2013-10-01

    申请号：US13738866

    申请日：2013-01-10

    Applicant: Intermolecular, Inc.

    Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Mitsuhiro Horikawa ,  Kenichi Koyanagi ,  Hiroyuki Ode ,  Xiangxin Rui

    IPC: H01L21/20 ,  H01L21/31

    CPC classification number: H01L28/60 ,  H01L28/40 ,  H01L28/75

    Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

    Abstract translation: 描述了制造DRAM电容器堆叠的方法，其中电介质材料是由与轻掺杂或非掺杂材料组合的高掺杂材料形成的多层叠层。 在退火步骤之后，高掺杂材料保持无定形，结晶含量小于30％。 在退火步骤之后，轻掺杂或非掺杂材料变成结晶含量等于或大于30％的晶体。 电介质多层堆叠保持高的k值，同时使漏电流和EOT值最小化。

    Methods for depositing high-K dielectrics
    29.
    发明授权
    Methods for depositing high-K dielectrics 有权
    沉积高K电介质的方法

    公开(公告)号：US08541828B2

    公开(公告)日：2013-09-24

    申请号：US13668488

    申请日：2012-11-05

    Applicant: Intermolecular, Inc.

    Inventor： Imran Hashim ,  Edward L. Haywood ,  Sandra G. Malhotra ,  Xiangxin Rui ,  Sunil Shanker

    IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC classification number: H01L21/3141 ,  C23C16/02 ,  C23C16/405 ,  H01L21/02186 ,  H01L21/02271 ,  H01L21/02315 ,  H01L21/31604 ,  H01L28/91

    Abstract: Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact angle of a surface of the metal, and depositing a titanium oxide layer on the exposed metal using at least one of a chemical vapor deposition process and an atomic layer deposition process, wherein the titanium oxide layer includes at least a portion of rutile titanium oxide.

    Abstract translation: 描述了用于沉积高K电介质的方法，包括在衬底上沉积第一电极，其中第一电极选自铂和钌，对暴露的金属施加氧等离子体处理以减小接触角 并且使用化学气相沉积工艺和原子层沉积工艺中的至少一种将氧化钛层沉积在暴露的金属上，其中氧化钛层包括至少一部分金红石型氧化钛。

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