Phase change memory devices and methods of forming the same
    21.
    发明授权
    Phase change memory devices and methods of forming the same 失效
    相变存储器件及其形成方法

    公开(公告)号:US07939366B2

    公开(公告)日:2011-05-10

    申请号:US12219647

    申请日:2008-07-25

    IPC分类号: H01L21/06

    摘要: A method of forming a phase change memory device includes forming a core pattern on a substrate, conformally forming a heat conductive layer on the substrate including the core pattern, anisotropically etching the heat conductive layer down to a top surface of the core pattern to form a heat electrode surrounding a sidewall of the core pattern, and forming a phase change memory pattern connected to a top surface of the heat electrode.

    摘要翻译: 形成相变存储器件的方法包括在衬底上形成芯图案,在包括芯图案的衬底上共形形成导热层,各向异性地将导热层刻蚀成芯图案的顶表面,以形成 围绕芯图案的侧壁的热电极,以及形成连接到热电极的顶表面的相变存储器图案。

    Semiconductor device having multi-layer oxygen barrier pattern
    22.
    发明授权
    Semiconductor device having multi-layer oxygen barrier pattern 失效
    具有多层氧阻挡图案的半导体器件

    公开(公告)号:US06956279B2

    公开(公告)日:2005-10-18

    申请号:US09956498

    申请日:2001-09-18

    申请人: Yoon-Jong Song

    发明人: Yoon-Jong Song

    摘要: The present invention relates to the field of a semiconductor device having a ferroelectric material capacitor and method of making the same. The semiconductor device includes a capacitor having a triple-level oxygen barrier layer pattern formed by an oxygen barrier metal layer, a material layer formed of a conductive solid solution by compounding the oxygen barrier metal layer and oxygen, and an oxygen barrier metal on an interlayer dielectric with a contact plug. The capacitor also has an electrode and a ferroelectric film electrically contacting to the oxygen barrier layer. Further, a wetting layer is formed between the oxygen barrier layer and the contact plug, and an iridium oxygen layer is formed between the oxygen barrier layer and a capacitor electrode.

    摘要翻译: 本发明涉及具有铁电材料电容器的半导体器件的领域及其制造方法。 该半导体器件包括具有由氧阻隔金属层形成的三层氧阻隔层图案的电容器,通过将氧阻隔金属层与氧混合而形成的导电固溶体的材料层和中间层上的阻氧金属 电介质与接触塞。 电容器还具有与氧阻隔层电接触的电极和铁电体膜。 此外,在氧阻隔层和接触塞之间形成润湿层,并且在氧阻隔层和电容器电极之间形成铱氧层。

    Ferroelectric memory device and method of forming the same
    23.
    发明授权
    Ferroelectric memory device and method of forming the same 失效
    铁电存储器件及其形成方法

    公开(公告)号:US06825082B2

    公开(公告)日:2004-11-30

    申请号:US10800273

    申请日:2004-03-11

    IPC分类号: H01L218242

    摘要: A ferroelectric memory device along with a method of forming the same are provided. A first interlayer insulating layer is formed on a semiconductor substrate. A buried contact structure is formed on the first interlayer insulating layer. The buried contact structure is electrically connected to the substrate through a first contact hole extending through the first interlayer insulating layer. A blocking layer covers or encapsulates the buried contact structure and the first interlayer insulating layer. A second interlayer insulating layer is formed on the blocking layer. A ferroelectric capacitor formed on the second interlayer insulating layer and is electrically connected to the buried contact structure through a second contact hole that penetrates the second interlayer insulating layer and the blocking layer.

    摘要翻译: 提供了一种铁电存储器件及其形成方法。 第一层间绝缘层形成在半导体衬底上。 在第一层间绝缘层上形成掩埋接触结构。 掩埋接触结构通过延伸穿过第一层间绝缘层的第一接触孔电连接至基板。 阻挡层覆盖或封装埋层接触结构和第一层间绝缘层。 在阻挡层上形成第二层间绝缘层。 形成在所述第二层间绝缘层上的铁电电容器,其通过贯穿所述第二层间绝缘层和所述阻挡层的第二接触孔与所述埋入触点结构电连接。

    Ferroelectric memory device using via etch-stop layer and method for manufacturing the same

    公开(公告)号:US06713310B2

    公开(公告)日:2004-03-30

    申请号:US10354651

    申请日:2003-01-29

    IPC分类号: H01G706

    CPC分类号: H01L27/11502 H01L27/11507

    摘要: A ferroelectric memory device and a method for manufacturing the same. The ferroelectric memory device comprises a lower interlayer insulating layer formed on a semiconductor substrate. The ferroelectric memory device further comprises at least two adjacent ferroelectric capacitors disposed on the lower interlayer insulating layer, an interlayer insulation layer formed over the ferroelectric capacitors, leaving a top surface of the ferroelectric capacitors exposed, a patterned via etch-stop layer formed on the interlayer insulation layer, leaving the top surface of the capacitors exposed, an upper interlayer insulating layer formed on the patterned via etch-stop layer, and a plate line commonly connected to the at least two adjacent ferroelectric capacitors. Thus, integration of the ferroelectric memory device can be substantially increased.

    Magnetic memory device and method for forming the same
    25.
    发明授权
    Magnetic memory device and method for forming the same 有权
    磁记忆装置及其形成方法

    公开(公告)号:US09484526B2

    公开(公告)日:2016-11-01

    申请号:US14656659

    申请日:2015-03-12

    摘要: Provided are a magnetic memory device and a method of forming the same. The magnetic memory device includes a magnetic tunnel junction pattern located on a substrate and including magnetic patterns and a tunnel barrier pattern located between the magnetic patterns, and a first crystallinity conserving pattern located on the magnetic tunnel junction pattern and having a higher crystallization temperature than the magnetic patterns. The first crystallinity conserving pattern is amorphous.

    摘要翻译: 提供一种磁存储器件及其形成方法。 磁存储器件包括位于衬底上的磁性隧道结图案,其包括磁性图案和位于磁性图案之间的隧道势垒图案,以及位于磁性隧道结图案上的第一结晶保存图案,并且具有比 磁性图案。 第一个结晶保存图案是无定形的。

    Phase-changeable memory devices having reduced susceptibility to thermal interference
    26.
    发明授权
    Phase-changeable memory devices having reduced susceptibility to thermal interference 有权
    相变型存储器件具有降低的对热干扰的敏感性

    公开(公告)号:US07977662B2

    公开(公告)日:2011-07-12

    申请号:US12265262

    申请日:2008-11-05

    IPC分类号: H01L29/06 H01L47/00

    摘要: A non-volatile memory array includes an array of phase-changeable memory elements that are electrically insulated from each other by at least a first electrically insulating region extending between the array of phase-changeable memory elements. The first electrically insulating region includes a plurality of voids therein. Each of these voids extends between a corresponding pair of phase-changeable memory cells in the non-volatile memory array and, collectively, the voids form an array of voids in the first electrically insulating region.

    摘要翻译: 非易失性存储器阵列包括相变存储元件的阵列,它们通过在可相变存储元件阵列之间延伸的至少第一电绝缘区域彼此电绝缘。 第一电绝缘区域中包括多个空隙。 这些空隙中的每一个在非易失性存储器阵列中相应的一对相位可变存储单元之间延伸,并且总体上空隙在第一电绝缘区域中形成一组空隙。

    PHASE CHANGE MEMORY DEVICES HAVING DUAL LOWER ELECTRODES AND METHODS OF FABRICATING THE SAME
    27.
    发明申请
    PHASE CHANGE MEMORY DEVICES HAVING DUAL LOWER ELECTRODES AND METHODS OF FABRICATING THE SAME 有权
    具有双下电极的相变存储器件及其制造方法

    公开(公告)号:US20100144090A1

    公开(公告)日:2010-06-10

    申请号:US12709536

    申请日:2010-02-22

    IPC分类号: H01L21/02

    摘要: A semiconductor device includes a semiconductor substrate and a lower interlayer insulating layer disposed on the substrate. An opening passing through the lower interlayer insulating layer and exposing the substrate is included. A buried insulating pattern is disposed in the opening. First and second conductive layer patterns are sequentially stacked to surround the sidewall and bottom of the buried insulating pattern. A phase change material pattern is included, which is disposed on the lower interlayer insulating layer in contact with a top surface of the second conductive layer pattern, and spaced apart from the first conductive layer pattern. An upper interlayer insulating layer covering the lower interlayer insulating layer and the phase change material pattern is included. A conductive plug is included, which passes through the upper interlayer insulating layer and is electrically connected to the phase change material pattern. A method of fabricating the semiconductor device is also provided.

    摘要翻译: 半导体器件包括半导体衬底和设置在衬底上的下层间绝缘层。 包括通过下层间绝缘层并露出衬底的开口。 掩埋绝缘图案设置在开口中。 依次堆叠第一和第二导电层图案以围绕埋入绝缘图案的侧壁和底部。 包括相变材料图案,其设置在与第二导电层图案的顶表面接触并且与第一导电层图案间隔开的下层间绝缘层上。 包括覆盖下层间绝缘层的上层间绝缘层和相变材料图案。 包括导电塞,其穿过上层间绝缘层并电连接到相变材料图案。 还提供了制造半导体器件的方法。

    Methods for fabricating ferroelectric memory devices with improved ferroelectric properties
    28.
    发明授权
    Methods for fabricating ferroelectric memory devices with improved ferroelectric properties 有权
    具有改进的铁电性能的制造铁电存储器件的方法

    公开(公告)号:US07488628B2

    公开(公告)日:2009-02-10

    申请号:US11384689

    申请日:2006-03-20

    摘要: Pursuant to embodiments of the present invention, ferroelectric memory devices are provided which comprise a transistor that is provided on an active region in a semiconductor substrate, and a capacitor that has a bottom electrode, a capacitor-ferroelectric layer and a top electrode. These devices may further include at least one planarizing layer that is adjacent to the side surfaces of the bottom electrode such that the top surface of the planarizing layer(s) and the top surface of the bottom electrode form a planar surface. The capacitor-ferroelectric may be formed on this planar surface. The device may also include a plug that electrically connects the bottom electrode to a source-drain region of the transistor. The ferroelectric memory devices according to embodiments of the present invention may reduce ferroelectric degradation of the capacitor.

    摘要翻译: 根据本发明的实施例,提供了包括设置在半导体衬底中的有源区上的晶体管和具有底电极,电容器 - 铁电层和顶电极的电容器的铁电存储器件。 这些装置还可以包括与底部电极的侧表面相邻的至少一个平坦化层,使得平坦化层的顶表面和底部电极的顶表面形成平坦的表面。 电容器 - 铁电体可以形成在该平坦表面上。 器件还可以包括将底部电极电连接到晶体管的源极 - 漏极区域的插头。 根据本发明实施例的铁电存储器件可以减小电容器的铁电性能降低。

    Methods for fabricating ferroelectric memory devices with improved ferroelectric properties

    公开(公告)号:US20060160252A1

    公开(公告)日:2006-07-20

    申请号:US11384689

    申请日:2006-03-20

    IPC分类号: H01L21/00 H01L21/8242

    摘要: Pursuant to embodiments of the present invention, ferroelectric memory devices are provided which comprise a transistor that is provided on an active region in a semiconductor substrate, and a capacitor that has a bottom electrode, a capacitor-ferroelectric layer and a top electrode. These devices may further include at least one planarizing layer that is adjacent to the side surfaces of the bottom electrode such that the top surface of the planarizing layer(s) and the top surface of the bottom electrode form a planar surface. The capacitor-ferroelectric may be formed on this planar surface. The device may also include a plug that electrically connects the bottom electrode to a source-drain region of the transistor. The ferroelectric memory devices according to embodiments of the present invention may reduce ferroelectric degradation of the capacitor.

    Ferroelectric memory devices having an expanded plate electrode
    30.
    发明授权
    Ferroelectric memory devices having an expanded plate electrode 失效
    具有扩展板电极的铁电存储器件

    公开(公告)号:US07064366B2

    公开(公告)日:2006-06-20

    申请号:US10787424

    申请日:2004-02-26

    摘要: Ferroelectric memory devices are formed on an integrated circuit substrate. A bottom interlayer dielectric layer is positioned on the integrated circuit substrate and a plurality of ferroelectric capacitors are arranged in a row and column relationship on the bottom interlayer dielectric layer. A top interlayer dielectric layer is disposed on a surface of the integrated circuit substrate including the plurality of ferroelectric capacitors. The top interlayer dielectric layer includes via holes disposed on and associated with ones of the ferroelectric capacitors. A plate electrode is formed in the top interlayer dielectric layer. The plate electrode extends into respective ones of the via holes to contact top surfaces of at least two neighboring ones of the plurality of ferroelectric capacitors. Methods or fabricating ferroelectric memory devices are also provided.

    摘要翻译: 铁电存储器件形成在集成电路衬底上。 底层间介质层位于集成电路基板上,并且多个铁电电容器以行和列关系布置在底层间介质层上。 在包括多个铁电电容器的集成电路基板的表面上设置顶层间介质层。 顶层间介质层包括布置在铁电电容器之一上并与其相关联的通孔。 在顶层间介质层中形成平板电极。 板电极延伸到相应的通孔中以接触多个铁电电容器中的至少两个相邻的电介质电容器的顶表面。 还提供了方法或制造铁电存储器件。