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    Composite core circuit module system and method
    22.
    发明授权
    Composite core circuit module system and method 有权
    复合核心电路模块系统及方法

    公开(公告)号：US07511969B2

    公开(公告)日：2009-03-31

    申请号：US11345910

    申请日：2006-02-02

    Applicant: James Douglas Wehrly, Jr.

    Inventor： James Douglas Wehrly, Jr.

    IPC: H05K1/11

    CPC classification number: H05K1/141 ,  H01L25/0655 ,  H01L2924/0002 ,  H05K1/117 ,  H05K1/144 ,  H05K1/181 ,  H05K2201/042 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2203/1572 ,  H01L2924/00

    Abstract: A circuit module is provided in which at least one secondary substrate and preferably two such secondary substrates are populated with integrated circuits (ICs). A rigid core substrate for the circuit module is comprised of a structural member and a connective member. In a preferred embodiment, the structural member is comprised of thermally conductive material while the connective member is comprised of conventional PWB material. The secondary substrate(s) are connected to the connective member with a variety of techniques and materials while, in a preferred embodiment, the connective member exhibits, in a preferred embodiment, traditional module contacts which provide an edge connector capability to allow the module to supplant traditional DIMMs.

    Abstract translation: 提供了一种电路模块，其中至少一个辅助衬底，优选地两个这样的辅助衬底填充有集成电路（IC）。 用于电路模块的刚性芯基板由结构构件和连接构件组成。 在优选实施例中，结构构件由导热材料构成，而连接构件由常规PWB材料构成。 第二基底通过各种技术和材料连接到连接构件，而在优选实施例中，在优选实施例中，连接构件表现出传统的模块触点，其提供边缘连接器能力以允许模块 取代传统DIMM。

    Active cooling methods and apparatus for modules
    25.
    发明授权
    Active cooling methods and apparatus for modules 失效
    主动冷却方式和模块装置

    公开(公告)号：US07289327B2

    公开(公告)日：2007-10-30

    申请号：US11364489

    申请日：2006-02-27

    Applicant: Paul Goodwin ,  James Douglas Wehrly, Jr.

    Inventor： Paul Goodwin ,  James Douglas Wehrly, Jr.

    IPC: H05K7/20 ,  F28D15/00

    CPC classification number: G11C5/00 ,  G06F1/20 ,  G11C5/143 ,  H01L23/427 ,  H01L23/473 ,  H01L2224/16 ,  H01L2224/73253

    Abstract: A circuit module that includes a system for reducing thermal variation and cooling the circuit module. In preferred embodiments, the module includes a thermally-conductive rigid substrate having first and second lateral sides, an edge, and an integrated cooling component. The integrated cooling component reduces thermal variation and cools the circuit module. Flex circuitry populated with a plurality of ICs and exhibiting a connective facility that comprises plural contacts for use with an edge connector is wrapped about the edge of the thermally-conductive substrate. Heat from the plurality of ICs is thermally-conducted by the thermally-conductive substrate to the integrated cooling component.

    Abstract translation: 一种电路模块，包括用于减少热变化并冷却电路模块的系统。 在优选实施例中，模块包括具有第一和第二横向侧面，边缘和集成冷却部件的导热刚性基板。 集成冷却组件减​​少热变化并冷却电路模块。 填充有多个IC并且展现包括用于边缘连接器的多个触点的连接设备的柔性电路围绕导热基板的边缘缠绕。 来自多个IC的热量被导热基板热传导到集成冷却部件。

    Memory expansion and chip scale stacking system and method
    26.
    发明授权
    Memory expansion and chip scale stacking system and method 失效
    内存扩展和芯片级堆叠系统及方法

    公开(公告)号：US07256484B2

    公开(公告)日：2007-08-14

    申请号：US10963867

    申请日：2004-10-12

    Applicant: Russell Rapport ,  James W. Cady ,  James Wilder ,  David L. Roper ,  James Douglas Wehrly, Jr. ,  Jeff Buchle

    Inventor： Russell Rapport ,  James W. Cady ,  James Wilder ,  David L. Roper ,  James Douglas Wehrly, Jr. ,  Jeff Buchle

    IPC: H01L23/02

    CPC classification number: H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/50 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2224/0401

    Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access. This favorably changes the impedance characteristics exhibited by a DIMM board populated with stacked modules. In a preferred embodiment, FET multiplexers for example, under logic control select particular data lines associated with particular levels of stacked modules populated upon a DIMM for connection to a controlling chip set in a memory expansion system.

    Abstract translation: 本发明将芯片级封装集成电路（CSP）堆叠成保存PWB或其他板表面积的模块。 在另一方面，本发明提供了一种较低电容存储器扩展寻址系统和方法，并且优选地具有本文提供的CSP堆叠模块。 在根据本发明的优选实施例中，形式标准被布置在柔性电路和IC封装之间，柔性电路的一部分放置在该IC封装上。 形式标准提供了一种物理形式，允许在采用标准连接柔性电路设计时，在广泛的CSP封装系列中发现许多变化的封装尺寸。 在优选实施例中，将设计形式标准，以便传热材料例如铜，以改善热性能。 在优选实施例中，高速交换系统选择与堆叠模块的每个级别相关联的数据线，以减少对存储器访问中的数据信号的负载效应。 这有利地改变了堆叠模块的DIMM板所呈现的阻抗特性。 在优选实施例中，例如在逻辑控制下的FET多路复用器选择与填充在DIMM上的特定级别的堆叠模块相关联的特定数据线，以连接到存储器扩展系统中的控制芯片。

    Low profile chip scale stacking system and method
    27.
    发明授权
    Low profile chip scale stacking system and method 有权
    薄型芯片级堆叠系统及方法

    公开(公告)号：US07094632B2

    公开(公告)日：2006-08-22

    申请号：US10873847

    申请日：2004-06-22

    Applicant: James W. Cady ,  Julian Partridge ,  James Douglas Wehrly, Jr. ,  James Wilder ,  David L. Roper ,  Jeff Buchle

    Inventor： James W. Cady ,  Julian Partridge ,  James Douglas Wehrly, Jr. ,  James Wilder ,  David L. Roper ,  Jeff Buchle

    IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

    CPC classification number: H05K1/141 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/81801 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/01322 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y10T29/49126 ,  Y10T29/49144

    Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile structures provide connection between CSPs of the stacked module and between and to the flex circuitry. Low profile contacts are created by any of a variety of methods and materials including, for example, screen paste techniques and use of high temperature solders, although other application techniques and traditional solders may be employed for creating low profile contacts in the present invention. A consolidated low profile contact structure and technique is provided for use in alternative embodiments of the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or two or more conductive layers. In some preferred embodiments, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In other embodiments, a heat spreader is disposed between the CSP and the flex circuitry thus providing an improved heat transference function without the standardization of the form standard, while still other embodiments lack either a form standard or a heat spreader and may employ, for example, the flex circuitry as a heat transference material.

    Abstract translation: 本发明将芯片级封装集成电路（CSP）堆叠成保留PWB或其他板表面积的低轮廓模块。 薄型结构提供堆叠模块的CSP之间和柔性电路之间的连接。 薄型触点由各种方法和材料中的任何一种产生，包括例如丝网糊技术和高温焊料的使用，尽管其它应用技术和传统焊料可用于在本发明中制造低轮廓触点。 提供了一种合并的低轮廓接触结构和技术，用于本发明的替代实施例。 根据本发明设计的堆叠模块中采用的CSP与柔性电路连接。 该柔性电路可以表现出一个或两个或更多个导电层。 在一些优选实施例中，形式标准提供了一种物理形式，其允许在采用标准连接柔性电路设计的同时，在广泛的CSP封装系列中发现许多变化的封装尺寸。 在其他实施例中，散热器设置在CSP和柔性电路之间，从而提供改进的热传递功能，而不需要形式标准的标准化，而其它实施例还没有形式标准或散热器，并且可以采用例如 ，柔性电路作为热转移材料。

    Pitch change and chip scale stacking system
    28.
    发明授权
    Pitch change and chip scale stacking system 有权
    间距变换和芯片级堆叠系统

    公开(公告)号：US07053478B2

    公开(公告)日：2006-05-30

    申请号：US10914483

    申请日：2004-08-09

    Applicant: David L. Roper ,  James W. Cady ,  James Wilder ,  James Douglas Wehrly, Jr. ,  Jeff Buchle ,  Julian Dowden

    Inventor： David L. Roper ,  James W. Cady ,  James Wilder ,  James Douglas Wehrly, Jr. ,  Jeff Buchle ,  Julian Dowden

    IPC: H01L23/02

    CPC classification number: H01L23/49816 ,  H01L23/3114 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734

    Abstract: The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two integrated circuits are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower integrated circuit of the module. The flex circuit pair connects the upper and lower integrated circuits and provides a thermal and electrical path connection path between the module and its application environment. The module has a ballout pattern with a different pitch and/or supplemental module contacts devised to allow combined signaling to the integrated circuits through contacts having a desired ballout footprint. The present invention may be employed to advantage in numerous configurations and combinations of integrated circuits in modules provided for high-density memories or high capacity computing.

    Abstract translation: 本发明将集成电路堆叠成节省电路板表面积的模块。 在根据本发明的优选实施例设计的两高堆叠或模块中，堆叠一对集成电路，一个集成电路在另一个之上。 两个集成电路与一对柔性电路结构连接。 一对柔性电路结构中的每一个部分地缠绕在模块的下部集成电路的相应的相对侧边缘上。 柔性电路对连接上下集成电路，并在模块与其应用环境之间提供热和电路连接路径。 模块具有不同间距和/或补充模块触点的布置图案，其设计为允许通过具有期望的展开占位面积的触点对集成电路的组合信令。 本发明可以有利于提供用于高密度存储器或高容量计算的模块中的集成电路的多种配置和组合。

    Memory card and method for devising
    30.
    发明授权
    Memory card and method for devising 有权
    存储卡和设计方法

    公开(公告)号：US07605454B2

    公开(公告)日：2009-10-20

    申请号：US11670396

    申请日：2007-02-01

    Applicant: James Douglas Wehrly, Jr.

    Inventor： James Douglas Wehrly, Jr.

    IPC: H01L23/02 ,  H01L21/48 ,  H01L23/04 ,  H01L23/34 ,  H01L23/52 ,  H01L29/40

    CPC classification number: H01L23/5387 ,  G06K19/07732 ,  H01L23/5388 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present invention provides a system and method for employing leaded packaged memory devices in memory cards. Leaded packaged ICs are disposed on one or both sides of a flex circuitry structure to create an IC-populated structure. In a preferred embodiment, leads of constituent leaded IC packages are configured to allowed the lower surface of the leaded IC packages to contact respective surfaces of the flex circuitry structure. Contacts for typical embodiments are supported by a rigid portion of the flex circuitry structure and the IC-populated structure is disposed in a casing to provide card structure for the module.

    Abstract translation: 本发明提供一种在存储卡中采用引线封装的存储器件的系统和方法。 引线封装IC布置在柔性电路结构的一侧或两侧以产生IC填充结构。 在优选实施例中，构成引线IC封装的引线被配置为允许引线IC封装的下表面接触柔性电路结构的相应表面。 用于典型实施例的触头由柔性电路结构的刚性部分支撑，并且IC填充结构设置在壳体中以为模块提供卡结构。

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