公开(公告)号：US08268683B2

公开(公告)日：2012-09-18

申请号：US12782859

申请日：2010-05-19

Applicant: Liang-Gi Yao ,  Chun-Hu Cheng ,  Chen-Yi Lee ,  Jeff J. Xu ,  Clement Hsingjen Wann

Inventor： Liang-Gi Yao ,  Chun-Hu Cheng ,  Chen-Yi Lee ,  Jeff J. Xu ,  Clement Hsingjen Wann

IPC: H01L21/8249

CPC classification number: H01L29/513 ,  H01L21/02172 ,  H01L21/022 ,  H01L21/28158 ,  H01L21/28211 ,  H01L21/283 ,  H01L29/42364 ,  H01L29/517 ,  H01L29/78

Abstract: A method for reducing interfacial layer (IL) thickness for high-k dielectrics and metal gate stack is provided. In one embodiment, the method includes forming an interfacial layer on a semiconductor substrate, etching back the interfacial layer, depositing a high-k dielectric material over the interfacial layer, and forming a metal gate over the high-k dielectric material. The IL can be chemical oxide, ozonated oxide, thermal oxide, or formed by ultraviolet ozone (UVO) oxidation process from chemical oxide, etc. The etching back of IL can be performed by a Diluted HF (DHF) process, a vapor HF process, or any other suitable process. The method can further include performing UV curing or low thermal budget annealing on the interfacial layer before depositing the high-k dielectric material.

Abstract translation: 提供了一种用于降低高k电介质和金属栅极叠层的界面层（IL）厚度的方法。 在一个实施例中，该方法包括在半导体衬底上形成界面层，蚀刻回界面层，在界面层上沉积高k电介质材料，以及在高k电介质材料上形成金属栅极。 IL可以是化学氧化物，臭氧化氧化物，热氧化物，或者由化学氧化物等的紫外线臭氧（UVO）氧化过程形成.II的回蚀可以通过稀释HF（DHF）工艺，蒸气HF工艺 ，或任何其他合适的过程。 该方法还可以包括在沉积高k介电材料之前在界面层上进行UV固化或低热预算退火。

公开(公告)号：US08241823B2

公开(公告)日：2012-08-14

申请号：US13248932

申请日：2011-09-29

Applicant: Ming-Feng Shieh ,  Shinn-Sheng Yu ,  Anthony Yen ,  Shao-Ming Yu ,  Chang-Yun Chang ,  Jeff J. Xu ,  Clement Hsingjen Wann

Inventor： Ming-Feng Shieh ,  Shinn-Sheng Yu ,  Anthony Yen ,  Shao-Ming Yu ,  Chang-Yun Chang ,  Jeff J. Xu ,  Clement Hsingjen Wann

IPC: G03G5/00 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L27/0203 ,  G03F1/00 ,  G03F1/36 ,  H01L21/3086 ,  H01L21/823431 ,  H01L29/66795

Abstract: Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region.

Abstract translation: 提供了一种包括光掩模的光刻设备。 光掩模包括具有多个特征的图案，在示例中为虚线特征。 该图案包括呈局部网格阵列形式的第一区域和其中至少一个特征具有增加的宽度的第二区域。 该装置可以包括可以限定有源区域的第二光掩模。 具有增加的宽度的特征可以与所定义的有效区域相邻并且在外部。

公开(公告)号：US08106469B2

公开(公告)日：2012-01-31

申请号：US12687574

申请日：2010-01-14

Applicant: Jeff J. Xu ,  Liang-Gi Yao ,  Ta-Ming Kuan

Inventor： Jeff J. Xu ,  Liang-Gi Yao ,  Ta-Ming Kuan

IPC: H01L21/02

CPC classification number: H01L21/2822 ,  H01L21/26506 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides methods and apparatus of fluorine passivation in IC device fabrication. In one embodiment, a method of fabricating a semiconductor device includes providing a substrate and passivating a surface of the substrate with a mixture of hydrofluoric acid and alcohol to form a fluorine-passivated surface. The method further includes forming a gate dielectric layer over the fluorine-passivated surface, and then forming a metal gate electrode over the gate dielectric layer. A semiconductor device fabricated by such a method is also disclosed.

Abstract translation: 本公开提供了IC器件制造中氟钝化的方法和装置。 在一个实施例中，制造半导体器件的方法包括提供衬底并用氢氟酸和醇的混合物钝化衬底的表面以形成氟钝化表面。 该方法还包括在氟钝化表面上形成栅极电介质层，然后在栅极介电层上形成金属栅电极。 还公开了通过这种方法制造的半导体器件。

公开(公告)号：US20120018785A1

公开(公告)日：2012-01-26

申请号：US13247507

申请日：2011-09-28

Applicant: Jeff J. Xu

Inventor： Jeff J. Xu

IPC: H01L29/78

CPC classification number: H01L29/66795

Abstract: The present disclosure provides a FinFET element. The FinFET element includes a germanium-FinFET element (e.g., a multi-gate device including a Ge-fin). In one embodiment, device includes a fin having a first portion including Ge and a second portion, underlying the first portion and including an insulating material (e.g., silicon dioxide). A gate structure may be formed on the fin.

Abstract translation: 本发明提供一种FinFET元件。 FinFET元件包括锗-FnFET元件（例如，包括Ge鳍的多栅极器件）。 在一个实施例中，装置包括翅片，其具有包括Ge和第二部分的第一部分，位于第一部分下方并且包括绝缘材料（例如，二氧化硅）。 可以在翅片上形成栅极结构。

公开(公告)号：US08039179B2

公开(公告)日：2011-10-18

申请号：US12980764

申请日：2010-12-29

Applicant: Ming-Feng Shieh ,  Shinn-Sheng Yu ,  Anthony Yen ,  Shao-Ming Yu ,  Chang-Yun Chang ,  Jeff J. Xu ,  Clement Hsingjen Wann

Inventor： Ming-Feng Shieh ,  Shinn-Sheng Yu ,  Anthony Yen ,  Shao-Ming Yu ,  Chang-Yun Chang ,  Jeff J. Xu ,  Clement Hsingjen Wann

IPC: G03C5/00 ,  G03F9/00

CPC classification number: H01L27/0203 ,  G03F1/00 ,  G03F1/36 ,  H01L21/3086 ,  H01L21/823431 ,  H01L29/66795

Abstract: Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality, of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region.

Abstract translation: 提供了一种包括光掩模的光刻设备。 光掩模包括具有多个特征的图案，在示例中为假线特征。 该图案包括呈局部网格阵列形式的第一区域和其中至少一个特征具有增加的宽度的第二区域。 该装置可以包括可以限定有源区域的第二光掩模。 具有增加的宽度的特征可以与所定义的有效区域相邻并且在外部。

公开(公告)号：US20100203734A1

公开(公告)日：2010-08-12

申请号：US12370152

申请日：2009-02-12

Applicant: Ming-Feng Shieh ,  Shinn-Sheng Yu ,  Anthony Yen ,  Ming-Ching Chang ,  Jeff J. Xu

Inventor： Ming-Feng Shieh ,  Shinn-Sheng Yu ,  Anthony Yen ,  Ming-Ching Chang ,  Jeff J. Xu

IPC: H01L21/467

CPC classification number: H01L21/3086 ,  H01L21/3088 ,  H01L21/823828 ,  H01L21/823871 ,  Y10S438/947

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a mask layer over a substrate, forming a dummy layer having a first dummy feature and a second dummy feature over the mask layer, forming first and second spacer roofs to cover a top portion of the first and second dummy features, respectively, and forming first and second spacer sleeves to encircle side portions of the first and second dummy features, respectively, removing the first spacer roof and the first dummy feature while protecting the second dummy feature, removing a first end portion and a second end portion of the first spacer sleeve to form spacer fins, and patterning the mask layer using the spacer fins as a first mask element and the second dummy feature as a second mask element.

Abstract translation: 本公开提供了一种制造半导体器件的方法，该半导体器件包括在衬底上形成掩模层，在掩模层上形成具有第一虚拟特征和第二虚拟特征的虚设层，形成第一和第二间隔物顶部以覆盖顶部 分别形成第一和第二间隔套筒以分别围绕第一和第二虚拟特征的侧面部分，去除第一间隔物顶部和第一虚拟特征，同时保护第二虚拟特征，去除 第一间隔套筒的第一端部和第二端部，以形成间隔件翅片，并且使用间隔件翅片作为第一掩模元件并将第二虚拟特征图案化为掩模层作为第二掩模元件。

公开(公告)号：US09166022B2

公开(公告)日：2015-10-20

申请号：US12917902

申请日：2010-11-02

Applicant: Jeff J. Xu ,  Chih-Hao Chang

Inventor： Jeff J. Xu ,  Chih-Hao Chang

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a first fin structure and a second fin structure over the semiconductor substrate; forming a gate structure over a portion of the first and second fin structures, such that the gate structure traverses the first and second fin structures; epitaxially growing a first semiconductor material on exposed portions of the first and second fin structures, such that the exposed portions of the first and second fin structures are merged together; and epitaxially growing a second semiconductor material over the first semiconductor material.

Abstract translation: 公开了一种用于制造FinFET器件的FinFET器件和方法。 一种示例性方法包括提供半导体衬底; 在半导体衬底上形成第一鳍结构和第二鳍结构; 在所述第一和第二鳍结构的一部分上形成栅极结构，使得所述栅极结构穿过所述第一鳍结构和所述第二鳍结构; 在第一和第二鳍结构的暴露部分上外延生长第一半导体材料，使得第一鳍结构和第二鳍结构的暴露部分合并在一起; 并且在所述第一半导体材料上外延生长第二半导体材料。

公开(公告)号：US09040393B2

公开(公告)日：2015-05-26

申请号：US13242090

申请日：2011-09-23

Applicant: Liang-Gi Yao ,  Chia-Cheng Chen ,  Ta-Ming Kuan ,  Jeff J. Xu ,  Clement Hsingjen Wann

Inventor： Liang-Gi Yao ,  Chia-Cheng Chen ,  Ta-Ming Kuan ,  Jeff J. Xu ,  Clement Hsingjen Wann

IPC: H01L21/20 ,  H01L21/265 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/02661 ,  H01L21/26506 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/2822 ,  H01L21/823418 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

Abstract: A method of forming a semiconductor device includes chemically cleaning a surface of a substrate to form a chemical oxide material on the surface. At least a portion of the chemical oxide material is removed at a removing rate of about 2 nanometer/minute (nm/min) or less. Thereafter, a gate dielectric layer is formed over the surface of the substrate.

Abstract translation: 形成半导体器件的方法包括化学清洗衬底的表面以在表面上形成化学氧化物材料。 化学氧化物材料的至少一部分以约2纳米/分钟（nm / min）或更小的去除速率除去。 此后，在衬底的表面上形成栅极电介质层。

公开(公告)号：US08629426B2

公开(公告)日：2014-01-14

申请号：US12960237

申请日：2010-12-03

Applicant: Chin-Hsiang Lin ,  Jeff J. Xu ,  Pang-Yen Tsai

Inventor： Chin-Hsiang Lin ,  Jeff J. Xu ,  Pang-Yen Tsai

IPC: H01L21/00

CPC classification number: H01L29/66575 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/7849

Abstract: Various source/drain stressors that can enhance carrier mobility, and methods for manufacturing the same, are disclosed. An exemplary source/drain stressor includes a seed layer of a first material disposed over a substrate of a second material, the first material being different than the second material; a relaxed epitaxial layer disposed over the seed layer; and an epitaxial layer disposed over the relaxed epitaxial layer.

Abstract translation: 公开了可以增强载流子迁移率的各种源极/漏极应力源及其制造方法。 示例性源极/漏极应力器包括设置在第二材料的衬底上的第一材料的种子层，第一材料不同于第二材料; 设置在种子层上的松弛外延层; 以及设置在松弛外延层上的外延层。

公开(公告)号：US08367534B2

公开(公告)日：2013-02-05

申请号：US12884500

申请日：2010-09-17

Applicant: Neng-Kuo Chen ,  Jeff J. Xu

Inventor： Neng-Kuo Chen ,  Jeff J. Xu

IPC: H01L21/20

CPC classification number: H01L21/02337 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/32115 ,  H01L21/32137

Abstract: Provided is a method of planarizing a semiconductor device. The method includes providing a substrate. The method includes forming a first layer over the substrate. The method includes forming a second layer over the first layer. The first and second layers have different material compositions. The method includes forming a third layer over the second layer. The method includes performing a polishing process on the third layer until the third layer is substantially removed. The method includes performing an etch back process to remove the second layer and a portion of the first layer. Wherein an etching selectivity of the etch back process with respect to the first and second layers is approximately 1:1.

Abstract translation: 提供了一种使半导体器件平坦化的方法。 该方法包括提供基板。 该方法包括在衬底上形成第一层。 该方法包括在第一层上形成第二层。 第一层和第二层具有不同的材料组成。 该方法包括在第二层上形成第三层。 该方法包括在第三层上进行抛光处理，直到第三层基本上被去除。 该方法包括执行回蚀处理以去除第二层和第一层的一部分。 其中相对于第一层和第二层的蚀刻返回工艺的蚀刻选择性为约1:1。