公开(公告)号：US20060160291A1

公开(公告)日：2006-07-20

申请号：US11039542

申请日：2005-01-19

申请人： Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas Tweet ,  Sheng Hsu

发明人： Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas Tweet ,  Sheng Hsu

IPC分类号： H01L21/8238

CPC分类号： H01L29/7842 ,  H01L21/76254 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/1203

摘要： A method of fabricating a biaxial tensile strained layer for NMOS fabrication and a uniaxial compressive strained layer for PMOS fabrication on a single wafer for use in CMOS ICs, includes preparing a silicon substrate for CMOS fabrication; depositing, patterning and etching a first and second insulating layers; removing a portion of the second insulating layer from a PMOS active area; depositing a layer of epitaxial silicon on the PMOS active area; removing a portion of the second insulating layer from an NMOS active area; growing an epitaxial silicon layer and growing an epitaxial SiGe layer on the NMOS active area; implanting H2+ ions; annealing the wafer to relax the SiGe layer; removing the remaining second insulating layer from the wafer; growing a layer of silicon; finishing a gate module; depositing a layer of SiO2 to cover the NMOS wafer; etching silicon in the PMOS active area; selectively growing a SiGe layer on the PMOS active area; wherein the silicon layer in the NMOS active area is under biaxial tensile strain, and the silicon layer in the PMOS active area is uniaxial compressive strained; and completing the CMOS device.

摘要翻译： 制造用于NMOS制造的双轴拉伸应变层的方法和用于CMOS IC的单个晶片上的用于PMOS制造的单轴压缩应变层包括制备用于CMOS制造的硅衬底; 沉积，图案化和蚀刻第一和第二绝缘层; 从PMOS有源区域去除所述第二绝缘层的一部分; 在PMOS有源区上沉积一层外延硅; 从NMOS有源区域去除所述第二绝缘层的一部分; 生长外延硅层并在NMOS有源区上生长外延SiGe层; 注入H 2 O 2 + + / - +离子; 退火晶片以松弛SiGe层; 从晶片上去除剩余的第二绝缘层; 生长一层硅; 完成门模块; 沉积SiO 2层以覆盖NMOS晶片; 蚀刻PMOS有源区中的硅; 在PMOS有源区上选择性地生长SiGe层; 其中所述NMOS有源区中的硅层处于双轴拉伸应变下，并且所述PMOS有源区中的硅层是单轴压缩应变的; 并完成CMOS设备。

公开(公告)号：US20060030124A1

公开(公告)日：2006-02-09

申请号：US10913677

申请日：2004-08-05

申请人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas Tweet ,  Sheng Hsu

发明人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas Tweet ,  Sheng Hsu

IPC分类号： H01L21/30 ,  H01L21/20

CPC分类号： H01L21/26506 ,  H01L21/187 ,  H01L21/6835 ,  H01L2221/6835 ,  H01L2221/68368 ,  Y10S438/977

摘要： A method of fabricating a silicon-on-plastic layer via layer transfer includes depositing a layer of SiGe on a silicon substrate; depositing a layer of silicon; implanting splitting hydrogen ions into the silicon substrate; bonding a glass substrate to the silicon layer; splitting the wafer; removing the silicon layer and a portion of the SiGe layer; depositing a dielectric on the silicon side of the silicon-on-glass wafer; applying adhesive and bonding a plastic substrate to the silicon side of the silicon-on-glass wafer; removing the glass from the glass side of the bonded, silicon-on-glass wafer to form a silicon-on-plastic wafer; and completing a desired IC device on the silicon-on-plastic. Multi-level structure may be fabricated according to the method of the invention by repeating the last few steps of the method of the invention.

摘要翻译： 通过层转移制造硅塑料层的方法包括在硅衬底上沉积SiGe层; 沉积一层硅; 将氢离子注入到硅衬底中; 将玻璃基板结合到硅层; 分裂晶片; 去除所述硅层和所述SiGe层的一部分; 在玻璃上硅晶片的硅侧沉积电介质; 施加粘合剂并将塑料基板粘合到硅玻璃晶片的硅侧; 从接合的硅玻璃晶片的玻璃面上移除玻璃以形成硅 - 硅晶片; 并在塑料硅胶上完成所需的IC器件。 可以通过重复本发明方法的最后几个步骤，根据本发明的方法制造多层结构。

公开(公告)号：US20050153474A1

公开(公告)日：2005-07-14

申请号：US10755567

申请日：2004-01-12

申请人： Douglas Tweet ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Hsu

发明人： Douglas Tweet ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Hsu

IPC分类号： G01J5/20 ,  H01L21/00 ,  H01L21/20 ,  H01L27/146 ,  H01L29/165 ,  H01L31/028 ,  H01L31/0352 ,  H01L31/10 ,  H01L31/109 ,  H01L31/18

CPC分类号： H01L31/105 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639 ,  H01L27/14627 ,  H01L27/14643 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/035281 ,  H01L31/108 ,  H01L31/109 ,  H01L31/1812 ,  Y02E10/547

摘要： Provided are a SiGe vertical optical path and a method for selectively forming a SiGe optical path normal structure for IR photodetection. The method comprises: forming a Si substrate surface; forming a Si feature, normal with respect to the Si substrate surface, such as a trench, via, or pillar; and, selectively forming a SiGe optical path overlying the Si normal feature. In some aspects, the Si substrate surface is formed a first plane and the Si normal feature has walls (sidewalls), normal with respect to the Si substrate surface, and a surface in a second plane, parallel to the first plane. Then, selectively forming a SiGe optical path overlying the Si normal feature includes forming a SiGe vertical optical path overlying the normal feature walls.

摘要翻译： 提供了SiGe垂直光路和用于选择性地形成用于IR光电检测的SiGe光路法线结构的方法。 该方法包括：形成Si衬底表面; 形成Si特征，相对于诸如沟槽，通孔或支柱的Si衬底表面是正常的; 并且选择性地形成覆盖Si正常特征的SiGe光路。 在一些方面，Si衬底表面形成第一平面，并且Si正常特征具有相对于Si衬底表面法线的壁（侧壁）和平行于第一平面的第二平面中的表面。 然后，选择性地形成覆盖Si正常特征的SiGe光路包括形成覆盖正常特征壁的SiGe垂直光路。

公开(公告)号：US20070218578A1

公开(公告)日：2007-09-20

申请号：US11384110

申请日：2006-03-17

申请人： Jong-Jan Lee ,  Sheng Hsu ,  Douglas Tweet ,  Jer-Shen Maa

发明人： Jong-Jan Lee ,  Sheng Hsu ,  Douglas Tweet ,  Jer-Shen Maa

IPC分类号： H01L21/00

CPC分类号： H01L27/14647

摘要： A CMOS active pixel sensor includes a silicon-on-insulator substrate having a silicon substrate with an insulator layer formed thereon and a top silicon layer formed on the insulator layer. A stacked pixel sensor cell includes a bottom photodiode fabricated on the silicon substrate, for sensing light of a longest wavelength; a middle photodiode fabricated on the silicon substrate, for sensing light of a medium wavelength, which is stacked above the bottom photodiode; and a top photodiode fabricated on the top silicon layer, for sensing light of a shorter wavelength, which is stacked above the middle and bottom photodiodes. Pixel transistor sets are fabricated on the top silicon layer and are associated with each pixel sensor cell by electrical connections which extend between each of the photodiodes and respective pixel transistor(s). CMOS control circuitry is fabricated adjacent to an array of active pixel sensor cells and electrically connected thereto.

摘要翻译： CMOS有源像素传感器包括具有在其上形成有绝缘体层的硅衬底和形成在绝缘体层上的顶部硅层的绝缘体上硅衬底。 层叠像素传感器单元包括：制造在硅衬底上的底部光电二极管，用于感测最长波长的光; 制造在硅衬底上的中间光电二极管，用于感测中等波长的光; 和制造在顶部硅层上的顶部光电二极管，用于感测较短波长的光，该光被层叠在中间和底部光电二极管的上方。 像素晶体管组被制造在顶部硅层上，并且通过在每个光电二极管和相应的像素晶体管之间延伸的电连接与每个像素传感器单元相关联。 CMOS控制电路与有源像素传感器单元的阵列相邻并且与其电连接。

公开(公告)号：US20070190681A1

公开(公告)日：2007-08-16

申请号：US11352724

申请日：2006-02-13

申请人： Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas Tweet ,  Sheng Hsu

发明人： Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas Tweet ,  Sheng Hsu

IPC分类号： H01L21/00

CPC分类号： H01L27/14649 ,  H01L27/14609 ,  H01L27/14689

摘要： A method is provided for forming a near infrared (NIR) active pixel sensor array on a silicon-on-insulator (SOI) substrate. The method forms a first wafer comprising a high resistance first Si substrate and a moderately doped first Si layer, and forms a second wafer comprising a first silicon oxide layer and a second Si layer. The method bonds the first wafer to the second wafer, forming a SOI substrate. Then, a diode is formed with a p-n junction space charge region extending into the first Si substrate. A thin-film transistor (TFT) is formed in the second Si layer, and interconnects are formed between the TFT and the diode. For example, first Si substrate may have a resistivity of greater than 100 ohm-cm, and the first Si layer may have a dopant concentration in the range of about 1×1016 to about 5×1018 cm−3.

摘要翻译： 提供了一种用于在绝缘体上硅（SOI）衬底上形成近红外（NIR）有源像素传感器阵列的方法。 该方法形成包括高电阻第一Si衬底和中度掺杂的第一Si层的第一晶片，并且形成包括第一氧化硅层和第二Si层的第二晶片。 该方法将第一晶片连接到第二晶片，形成SOI衬底。 然后，形成具有延伸到第一Si衬底中的p-n结空间电荷区域的二极管。 在第二Si层中形成薄膜晶体管（TFT），并且在TFT和二极管之间形成互连。 例如，第一Si衬底可以具有大于100欧姆 - 厘米的电阻率，并且第一Si层可以具有在约1×10 16至约5×10 18范围内的掺杂剂浓度， / SUP> cm 3 -3。

公开(公告)号：US20070099329A1

公开(公告)日：2007-05-03

申请号：US11260955

申请日：2005-10-27

申请人： Jer-Shen Maa ,  Jong-Jan Lee ,  Sheng Hsu ,  Douglas Tweet

发明人： Jer-Shen Maa ,  Jong-Jan Lee ,  Sheng Hsu ,  Douglas Tweet

IPC分类号： H01L21/00

CPC分类号： H01L31/1808 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02647 ,  H01L31/105 ,  Y02E10/50

摘要： A method of fabricating a germanium photo detector includes preparing a silicon substrate; depositing and planarizing a silicon oxide layer; forming contact holes in the silicon oxide layer which communicate with the underlying silicon substrate; growing an epitaxial germanium layer of a first type on the silicon oxide layer and in the contact holes; growing an intrinsic germanium layer on the epitaxial germanium layer and any exposed silicon oxide layer; growing a germanium layer of a second type on the intrinsic germanium layer and any exposed silicon oxide layer; depositing a layer of covering material take from the group of materials consisting of polysilicon, polysilicon-germanium and In2O3—SnO2; and etching the covering material to form individual sensing elements.

摘要翻译： 制造锗光电检测器的方法包括制备硅衬底; 沉积和平坦化氧化硅层; 在氧化硅层中形成与底层硅衬底连通的接触孔; 在氧化硅层和接触孔中生长第一类型的外延锗层; 在外延锗层和任何暴露的氧化硅层上生长内在的锗层; 在内部锗层和任何暴露的氧化硅层上生长第二类型的锗层; 沉积一层覆盖材料取自由多晶硅，多晶硅 - 锗和In 2 N 3 O 3 -SnO 2 2组成的材料组。 并蚀刻覆盖材料以形成单独的感测元件。

公开(公告)号：US20060194357A1

公开(公告)日：2006-08-31

申请号：US11240969

申请日：2005-09-30

申请人： Sheng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas Tweet

发明人： Sheng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas Tweet

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L31/1126 ,  C30B19/00 ,  C30B29/08 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02623 ,  H01L21/02639 ,  H01L21/30625 ,  H01L21/7624 ,  H01L27/14683 ,  H01L27/14689 ,  H01L29/16 ,  H01L29/78 ,  H01L31/105 ,  H01L31/1804 ,  H01L31/1808 ,  Y02E10/547

摘要： A high-density Germanium (Ge)-on-Insulator (GOI) photodiode array and corresponding fabrication method are provided. The method includes: forming an array of pixel driver nMOST devices, each device having a gate connected to a row line in a first orientation, a first source/drain (S/D) region, and a second S/D region connected to Vdd; forming a P-I-N Ge diode for each pixel as follows: forming a n+ region; forming an intrinsic Ge region overlying the n+ region; forming a p+ junction in the intrinsic Ge; and, isolating the P-I-N Ge diodes; and, forming an Indium Tin oxide (ITO) column in a second orientation, about orthogonal to the first orientation, overlying the P-I-N Ge diodes.

摘要翻译： 提供了高密度锗（Ge）绝缘体（GOI）光电二极管阵列和相应的制造方法。 该方法包括：形成像素驱动器nMOST器件的阵列，每个器件具有以第一取向连接到行线的栅极，第一源极/漏极（S / D）区域和连接到Vdd的第二S / D区域 ; 如下形成每个像素的P-I-N Ge二极管：形成n +区; 形成覆盖n +区域的本征Ge区域; 在本征Ge中形成p +结; 并隔离P-I-N Ge二极管; 并且以与第一取向正交的第二取向形成铟锡氧化物（ITO）柱，覆盖P-I-N Ge二极管。

公开(公告)号：US20060110844A1

公开(公告)日：2006-05-25

申请号：US10993533

申请日：2004-11-19

申请人： Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Hsu ,  Douglas Tweet

发明人： Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Hsu ,  Douglas Tweet

IPC分类号： H01L21/00

CPC分类号： H01L31/1804 ,  H01L21/187 ,  H01L21/76254 ,  H01L27/1443 ,  H01L31/02327 ,  H01L31/105 ,  Y02E10/547 ,  Y02P70/521

摘要： A method of fabricating a thin film germanium photodetector includes preparing a silicon substrate; fabricating a CMOS device on the silicon substrate; preparing a germanium substrate; preparing surfaces of each substrate for bonding; bonding the germanium substrate to the CMOS-bearing silicon substrate to form a bonded structure; removing a portion of the germanium substrate from the bonded structure; forming a PIN diode in the germanium substrate; removing a portion of the germanium layer by etching; and completing the germanium photo detector.

摘要翻译： 制造薄膜锗光电探测器的方法包括制备硅衬底; 在硅衬底上制造CMOS器件; 制备锗衬底; 准备每个基板的表面以进行接合; 将锗衬底结合到具有CMOS的硅衬底以形成结合结构; 从结合结构去除锗衬底的一部分; 在锗衬底中形成PIN二极管; 通过蚀刻去除锗层的一部分; 并完成锗光电检测器。

公开(公告)号：US20050151134A1

公开(公告)日：2005-07-14

申请号：US11073185

申请日：2005-03-03

申请人： Sheng Hsu ,  Jong-Jan Lee ,  Douglas Tweet ,  Jer-shen Maa

发明人： Sheng Hsu ,  Jong-Jan Lee ,  Douglas Tweet ,  Jer-shen Maa

IPC分类号： H01L21/322 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  H01L31/036

CPC分类号： H01L29/1054 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/78645

摘要： A dual gate strained-Si MOSFET with thin SiGe dislocation regions and a method for fabricating the same are provided. The method comprises: forming a first layer of relaxed SiGe overlying a substrate, having a thickness of less than 5000 Å; forming a second layer of relaxed SiGe overlying the substrate and adjacent to the first layer of SiGe, having a thickness of less than 5000 Å; forming a layer of strained-Si overlying the first and second SiGe layers; forming a shallow trench isolation region interposed between the first SiGe layer and the second SiGe layer; forming an n-well in the substrate and the overlying first layer of SiGe; forming a p-well in the substrate and the overlying second layer of SiGe; forming channel regions, in the strained-Si, and forming PMOS and NMOS transistor source and drain regions.

摘要翻译： 提供具有薄SiGe位错区域的双栅应变Si MOSFET及其制造方法。 该方法包括：形成覆盖衬底的第一层松弛SiGe，厚度小于5000; 形成第二层弛豫的SiGe，覆盖衬底并与第一层SiGe相邻，厚度小于5000; 形成层叠在第一和第二SiGe层上的应变层; 形成介于所述第一SiGe层和所述第二SiGe层之间的浅沟槽隔离区域; 在衬底和上覆的第一层SiGe中形成n阱; 在衬底和SiGe的上覆第二层中形成p阱; 在应变Si中形成沟道区，并形成PMOS和NMOS晶体管的源极和漏极区。

公开(公告)号：US20060051960A1

公开(公告)日：2006-03-09

申请号：US10936400

申请日：2004-09-07

申请人： Douglas Tweet ,  David Evans ,  Sheng Hsu ,  Jer-Shen Maa

发明人： Douglas Tweet ,  David Evans ,  Sheng Hsu ,  Jer-Shen Maa

IPC分类号： H01L21/44

CPC分类号： H01L21/02694 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L29/1054 ,  Y10S438/933

摘要： A method of forming a relaxed SiGe layer having a high germanium content in a semiconductor device includes preparing a silicon substrate; depositing a strained SiGe layer; implanting ions into the strained SiGe layer, wherein the ions include silicon ions and ions selected from the group of ions consisting of boron and helium, and which further includes implanting H+ ions; annealing to relax the strained SiGe layer, thereby forming a first relaxed SiGe layer; and completing the semiconductor device.

摘要翻译： 在半导体器件中形成具有高锗含量的弛豫SiGe层的方法包括制备硅衬底; 沉积应变SiGe层; 将离子注入到应变SiGe层中，其中离子包括选自由硼和氦构成的离子组的硅离子和离子，并且还包括注入H +离子; 退火以使应变SiGe层松弛，从而形成第一弛豫SiGe层; 并完成半导体器件。