利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

41 条记录 (耗时 0.035 秒)

    Etch stop and hard mask film property matching to enable improved replacement metal gate process
    21.
    发明授权
    Etch stop and hard mask film property matching to enable improved replacement metal gate process 有权

    公开(公告)号：US07271045B2

    公开(公告)日：2007-09-18

    申请号：US11240839

    申请日：2005-09-30

    申请人： Matthew J. Prince ,  Chris E. Barns ,  Justin K. Brask

    发明人： Matthew J. Prince ,  Chris E. Barns ,  Justin K. Brask

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/31111 ,  H01L29/66545 ,  Y10S438/926

    摘要： A method including forming a hard mask and an etch stop layer over a sacrificial material patterned as a gate electrode, wherein a material for the hard mask and a material for the etch stop layer are selected to have a similar stress property; removing the material for the hard mask and the material for the etch stop layer sufficient to expose the sacrificial material; replacing the sacrificial material with another material. A system including a computing device including a microprocessor, the microprocessor including a plurality of transistor devices, at least one of the plurality of transistor devices including a gate electrode formed on a substrate surface; a discontinuous etch stop layer conformally formed on the substrate surface and adjacent side wall surfaces of the gate electrode; and a dielectric material conformally formed over the etch stop layer.

    Preventing silicide formation at the gate electrode in a replacement metal gate technology
    23.
    发明授权
    Preventing silicide formation at the gate electrode in a replacement metal gate technology 失效
    在替代金属栅极技术中防止栅电极处的硅化物形成

    公开(公告)号：US07754552B2

    公开(公告)日：2010-07-13

    申请号：US10629127

    申请日：2003-07-29

    申请人： Chris E. Barns ,  Justin K. Brask ,  Mark Doczy

    发明人： Chris E. Barns ,  Justin K. Brask ,  Mark Doczy

    IPC分类号： H01L21/338

    CPC分类号： H01L29/66545

    摘要： A hard mask may be formed and maintained over a polysilicon gate structure in a metal gate replacement technology. The maintenance of the hard mask, such as a nitride hard mask, may protect the polysilicon gate structure 14 from the formation of silicide or etch byproducts. Either the silicide or the etch byproducts or their combination may block the ensuing polysilicon etch which is needed to remove the polysilicon gate structure and to thereafter replace it with an appropriate metal gate technology.

    摘要翻译： 在金属栅极替换技术中，可以在多晶硅栅极结构上形成并保持硬掩模。 硬掩模（例如氮化物硬掩模）的维护可以保护多晶硅栅极结构14免受硅化物或蚀刻副产物的形成。 硅化物或蚀刻副产物或它们的组合可以阻止除去多晶硅栅极结构所需的随后的多晶硅蚀刻，然后用适当的金属栅极技术代替它。

    Work piece wand and method for processing work pieces using a work piece handling wand
    26.
    发明授权
    Work piece wand and method for processing work pieces using a work piece handling wand 失效

    公开(公告)号：US06558562B2

    公开(公告)日：2003-05-06

    申请号：US09948836

    申请日：2001-09-07

    申请人： Daniel S. Mallery ,  Doug Kreager ,  Chris E. Barns

    发明人： Daniel S. Mallery ,  Doug Kreager ,  Chris E. Barns

    IPC分类号： B44C122

    CPC分类号： H01L21/68707 ,  G11B23/00

    摘要： A wafer handling wand allows the efficient loading and unloading of semiconductor wafers to and from a CMP apparatus. The wand includes identical work piece gripping, alignment, and loading/unloading mechanisms on the top and bottom sides. A processed wafer can be unloaded from the apparatus onto one side of the wand and an unprocessed wafer can be loaded into the apparatus from the second side. The gripping mechanism includes a support area and a spaced apart moveable gripping finger. Wafer loading is facilitated by a cam attached to the support area that rotates when the cam contacts the apparatus. Upon rotation, the cam provides a surface for directing the work piece into the apparatus. The surface of the cam also includes an alignment aid that can be brought into contact with a reference surface on the apparatus to insure proper alignment between the wand and the apparatus.

    Poly open polish process
    27.
    发明授权
    Poly open polish process 有权
    多孔开放抛光工艺

    公开(公告)号：US07166506B2

    公开(公告)日：2007-01-23

    申请号：US11015151

    申请日：2004-12-17

    申请人： Matthew J. Prince ,  Francis M. Tambwe ,  Chris E. Barns

    发明人： Matthew J. Prince ,  Francis M. Tambwe ,  Chris E. Barns

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/31053 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method of fabricating microelectronic structure using at least two material removal steps, such as for in a poly open polish process, is disclosed. In one embodiment, the first removal step may be chemical mechanical polishing (CMP) step utilizing a slurry with high selectivity to an interlevel dielectric layer used relative to an etch stop layer abutting a transistor gate. This allows the first CMP step to stop after contacting the etch stop layer, which results in substantially uniform “within die”, “within wafer”, and “wafer to wafer” topography. The removal step may expose a temporary component, such as a polysilicon gate within the transistor gate structure. Once the polysilicon gate is exposed other processes may be employed to produce a transistor gate having desired properties.

    摘要翻译： 公开了一种使用至少两种材料去除步骤制造微电子结构的方法，例如在多孔开式抛光工艺中。 在一个实施例中，第一去除步骤可以是利用相对于邻接晶体管栅极的蚀刻停止层使用的层间介电层具有高选择性的浆料的化学机械抛光（CMP）步骤。 这允许第一CMP步骤在接触蚀刻停止层之后停止，这导致基本上均匀的“在晶片内”，“在晶片内”和“晶片到晶片”形态。 去除步骤可以暴露诸如晶体管栅极结构内的多晶硅栅极的临时元件。 一旦多晶硅栅极被暴露，可以采用其它工艺来产生具有期望特性的晶体管栅极。

    Polysilicon opening polish
    28.
    发明授权
    Polysilicon opening polish 有权

    公开(公告)号：US06743683B2

    公开(公告)日：2004-06-01

    申请号：US10008683

    申请日：2001-12-04

    申请人： Chris E. Barns ,  Mark Doczy

    发明人： Chris E. Barns ,  Mark Doczy

    IPC分类号： H01L21336

    CPC分类号： H01L29/66545 ,  H01L21/3212 ,  H01L29/495

    摘要： Fabricating a semiconductor structure includes providing a semiconductor substrate, forming a silicide layer over the substrate, and removing a portion of the silicide layer by chemical mechanical polishing. The fabrication of the structure can also include forming a dielectric layer after forming the silicide layer, and removing a portion of the dielectric layer by chemical mechanical polishing before removing the portion of the silicide layer.

    Semiconductor wafer polishing apparatus with a flexible carrier plate
    29.
    发明授权
    Semiconductor wafer polishing apparatus with a flexible carrier plate 失效
    具有柔性载体板的半导体晶片抛光装置

    公开(公告)号：US5851140A

    公开(公告)日：1998-12-22

    申请号：US800941

    申请日：1997-02-13

    申请人： Chris E. Barns ,  Malek Charif ,  Kenneth D. Lefton ,  Fred E. Mitchel

    发明人： Chris E. Barns ,  Malek Charif ,  Kenneth D. Lefton ,  Fred E. Mitchel

    IPC分类号： H01L21/683 ,  B24B37/30 ,  B24B37/32 ,  H01L21/304 ,  B24B5/00

    CPC分类号： B24B37/30 ,  B24B37/32

    摘要： A carrier head for a semiconductor wafer polishing apparatus includes a rigid plate which has a major surface with a plurality of open fluid channels. A flexible wafer carrier membrane has a perforated wafer contact section for contacting the semiconductor wafer, and a bellows extending around the wafer contact section. A retaining ring is secured to the rigid plate with a flange on the bellows sandwiched between the plate's major surface and the retaining ring, thereby defining a cavity between the wafer carrier membrane and the rigid plate. A fluid conduit is coupled to the rigid plate allowing a source of a vacuum and a source of pressurized fluid alternately to be connected to the cavity.

    摘要翻译： 用于半导体晶片抛光装置的载体头包括具有主表面和多个开放流体通道的刚性板。 柔性晶片载体膜具有用于接触半导体晶片的穿孔晶片接触部分和围绕晶片接触部分延伸的波纹管。 保持环被固定到刚性板上，其中凸缘夹在板的主表面和保持环之间的波纹管上，从而在晶片载体膜和刚性板之间形成空腔。 流体导管联接到刚性板，允许真空源和加压流体源交替地连接到空腔。

    Thin III-V semiconductor films with high electron mobility
    30.
    发明申请
    Thin III-V semiconductor films with high electron mobility 审中-公开
    具有高电子迁移率的薄III-V半导体膜

    公开(公告)号：US20080132081A1

    公开(公告)日：2008-06-05

    申请号：US11633953

    申请日：2006-12-04

    申请人： Mohamad A. Shaheen ,  Mantu K. Hudait ,  Willy Rachmady ,  Jack T. Kavalieros ,  Chris E. Barns

    发明人： Mohamad A. Shaheen ,  Mantu K. Hudait ,  Willy Rachmady ,  Jack T. Kavalieros ,  Chris E. Barns

    IPC分类号： H01L21/00

    CPC分类号： H01L21/0254 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/02398 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549

    摘要： A method of forming a thin III-V semiconductor film on a semiconductor substrate, where the lattice structure of the III-V film is different than the lattice structure of the substrate. The method includes epitaxially growing the III-V film on the substrate until the III-V film is greater than 3.0 μm thick and then removing a portion of the III-V film until it is less than 3.0 μm thick. In one implementation, the III-V film is grown until it is around 8.0 μm to 10.0 μm thick, and then it is etched or polished until its thickness is reduced to 0.1 μm to 3.0 μm thick. By over-growing the III-V film, effects such as dislocation gliding and annihilation reduce the dislocation density of the film, thereby improving its electric mobility.

    摘要翻译： 在半导体衬底上形成薄的III-V半导体膜的方法，其中III-V膜的晶格结构不同于衬底的晶格结构。 该方法包括在衬底上外延生长III-V膜，直到III-V膜大于3.0μm厚，然后除去一部分III-V膜，直到其小于3.0μm厚。 在一个实施方案中，III-V膜生长直到其厚度约为8.0μm至10.0μm，然后进行蚀刻或抛光，直到其厚度减小至0.1μm至3.0μm厚。 通过过度生长III-V膜，如位错滑动和湮灭等作用降低了膜的位错密度，从而提高了其电迁移率。