公开(公告)号：US6040248A

公开(公告)日：2000-03-21

申请号：US104032

申请日：1998-06-24

申请人： Chao-Cheng Chen ,  Ming-Hsin Huang ,  Hun-Jan Tao ,  Chia-Shiung Tsai

发明人： Chao-Cheng Chen ,  Ming-Hsin Huang ,  Hun-Jan Tao ,  Chia-Shiung Tsai

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/302 ,  C23F1/02 ,  H01L21/461

CPC分类号： H01L21/31138 ,  H01L21/76802

摘要： A process for plasma etching of contact and via openings in low-k organic polymer dielectric layers is described which overcomes problems of sidewall bowing and hardmask pattern deterioration by etching the organic layer in a high density plasma etcher with a chlorine/inert gas plasma. By adding chlorine to the oxygen/inert gas plasma, the development of an angular aspect or faceting of the hardmask pattern edges by ion bombardment is abated. Essentially vertical sidewalls are obtained in the openings etched in the organic polymer layer while hardmask pattern integrity is maintained. The addition of a passivating agent such as nitrogen, BCl.sub.3, or CHF.sub.3 to the etchant gas mixture further improves the sidewall profile by reducing bowing through protective polymer formation.

摘要翻译： 描述了一种用于等离子体蚀刻低k有机聚合物介电层中的接触和通孔开口的方法，其通过用氯/惰性气体等离子体在高密度等离子体蚀刻机中蚀刻有机层来克服侧壁弯曲和硬掩模图案劣化的问题。 通过向氧/惰性气体等离子体中加入氯，减少了通过离子轰击形成硬掩模图案边缘的角度方面或刻面。 在保持硬掩模图案完整性的同时，在有机聚合物层中蚀刻的开口中获得基本垂直的侧壁。 钝化剂如氮气，BCl3或CHF3添加到蚀刻剂气体混合物中，通过减少通过保护性聚合物形成的弯曲来进一步改善侧壁轮廓。

公开(公告)号：US09991375B2

公开(公告)日：2018-06-05

申请号：US13484047

申请日：2012-05-30

申请人： Jr-Jung Lin ,  Chih-Han Lin ,  Jin-Aun Ng ,  Ming-Ching Chang ,  Chao-Cheng Chen

发明人： Jr-Jung Lin ,  Chih-Han Lin ,  Jin-Aun Ng ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC分类号： H01L29/78 ,  H01L21/283 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8238

CPC分类号： H01L29/78 ,  H01L21/283 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66545

摘要： The invention relates to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first rectangular gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first rectangular gate electrode; and a second dielectric material adjacent to the other 3 sides of the first rectangular gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first rectangular gate electrode.

公开(公告)号：US09595443B2

公开(公告)日：2017-03-14

申请号：US13277642

申请日：2011-10-20

申请人： Ming Zhu ,  Hui-Wen Lin ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Yuan-Sheng Huang ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen ,  Kuo-Cheng Ching ,  Ting-Hua Hsieh ,  Carlos H. Diaz

发明人： Ming Zhu ,  Hui-Wen Lin ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Yuan-Sheng Huang ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen ,  Kuo-Cheng Ching ,  Ting-Hua Hsieh ,  Carlos H. Diaz

IPC分类号： H01L21/70 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/42376 ,  H01L29/4966

摘要： The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising an isolation region surrounding and separating a P-active region and an N-active region; a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and an oxygen-containing TiN layer between the P-work function metal and substrate; and an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer connects to the oxygen-containing TiN layer over the isolation region.

摘要翻译： 本发明涉及集成电路制造，更具体地涉及一种金属栅极结构。 CMOS半导体器件的示例性结构包括：衬底，包括围绕并分离P活性区域和N-有源区域的隔离区域; 在P-活性区域上的P金属栅电极，并且在隔离区域上延伸，其中P金属栅电极包括P功函数金属和P功函数金属与衬底之间的含氧TiN层; 以及N型金属栅电极，其在N-有源区上方并在隔离区上方延伸，其中N型金属栅电极包括N功函数金属和N功函数金属与衬底之间的富氮TiN层 其中富氮TiN层在隔离区域上连接到含氧TiN层。

公开(公告)号：US09355874B2

公开(公告)日：2016-05-31

申请号：US13244337

申请日：2011-09-24

申请人： Weibo Yu ,  Hsueh-Chin Lu ,  Han-Guan Chew ,  Kuo Bin Huang ,  Chao-Cheng Chen ,  Syun-Ming Jang

发明人： Weibo Yu ,  Hsueh-Chin Lu ,  Han-Guan Chew ,  Kuo Bin Huang ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC分类号： C03C15/00 ,  H01L21/67 ,  H01L21/311

CPC分类号： H01L21/6708 ,  H01L21/31111

摘要： A single wafer etching apparatus and various methods implemented in the single wafer etching apparatus are disclosed. In an example, etching a silicon nitride layer in a single wafer etching apparatus includes: heating a phosphoric acid to a first temperature; heating a sulfuric acid to a second temperature; mixing the heated phosphoric acid and the heated sulfuric acid; heating the phosphoric acid/sulfuric acid mixture to a third temperature; and etching the silicon nitride layer with the heated phosphoric acid/sulfuric acid mixture.

摘要翻译： 公开了在单晶片蚀刻装置中实现的单晶片蚀刻装置和各种方法。 在一个实施例中，在单晶片蚀刻装置中蚀刻氮化硅层包括：将磷酸加热至第一温度; 将硫酸加热至第二温度; 混合加热的磷酸和加热的硫酸; 将磷酸/硫酸混合物加热至第三温度; 并用加热的磷酸/硫酸混合物蚀刻氮化硅层。

公开(公告)号：US08932936B2

公开(公告)日：2015-01-13

申请号：US13449118

申请日：2012-04-17

申请人： Chia-Chu Liu ,  Kuei-Shun Chen ,  Chih-Hsiung Peng ,  Chi-Kang Chang ,  Chiang Mu-Chi ,  Sheng-Yu Chang ,  Hua Feng Chen ,  Chao-Cheng Chen ,  Ryan Chia-Jen Chen

发明人： Chia-Chu Liu ,  Kuei-Shun Chen ,  Chih-Hsiung Peng ,  Chi-Kang Chang ,  Chiang Mu-Chi ,  Sheng-Yu Chang ,  Hua Feng Chen ,  Chao-Cheng Chen ,  Ryan Chia-Jen Chen

IPC分类号： H01L21/00

CPC分类号： H01L21/3086 ,  H01L21/76224

摘要： A method for fabricating a device is disclosed. An exemplary method includes providing a substrate and forming a plurality of fins over the substrate. The method further includes forming a first opening in the substrate in a first longitudinal direction. The method further includes forming a second opening in the substrate in a second longitudinal direction. The first and second longitudinal directions are different. The method further includes depositing a filling material in the first and second openings.

摘要翻译： 公开了一种制造装置的方法。 一种示例性的方法包括提供衬底并在衬底上形成多个鳍。 该方法还包括在第一纵向方向上在基板中形成第一开口。 该方法还包括在第二纵向方向上在基板中形成第二开口。 第一和第二纵向是不同的。 该方法还包括在第一和第二开口中沉积填充材料。

公开(公告)号：US20130187235A1

公开(公告)日：2013-07-25

申请号：US13353975

申请日：2012-01-19

申请人： Yuan-Sheng Huang ,  Tzu-Yen Hsieh ,  Ming-Ching Chang ,  Chao-Cheng Chen ,  Chia-Jen Chen

发明人： Yuan-Sheng Huang ,  Tzu-Yen Hsieh ,  Ming-Ching Chang ,  Chao-Cheng Chen ,  Chia-Jen Chen

IPC分类号： H01L27/092 ,  H01L21/28

CPC分类号： H01L29/66545 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

摘要： The present disclosure involves a FinFET. The FinFET includes a fin structure formed over a substrate. A gate dielectric layer is least partially wrapped around a segment of the fin structure. The gate dielectric layer contains a high-k gate dielectric material. The FinFET includes a polysilicon layer conformally formed on the gate dielectric layer. The FinFET includes a metal gate electrode layer formed over the polysilicon layer. The present disclosure provides a method of fabricating a FinFET. The method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a polysilicon layer over the gate dielectric layer, wherein the polysilicon layer is formed in a conformal manner. The method includes forming a dummy gate layer over the polysilicon layer.

摘要翻译： 本公开涉及FinFET。 FinFET包括在衬底上形成的翅片结构。 栅介质层最少部分地缠绕在翅片结构的一段上。 栅介质层包含高k栅介质材料。 FinFET包括在栅介质层上共形形成的多晶硅层。 FinFET包括在多晶硅层上形成的金属栅极电极层。 本公开提供了制造FinFET的方法。 该方法包括提供包含半导体材料的翅片结构。 该方法包括在鳍结构上方形成栅极电介质层，栅介质层至少部分地围绕翅片结构缠绕。 该方法包括在栅介质层上形成多晶硅层，其中多晶硅层以保形方式形成。 该方法包括在多晶硅层上形成伪栅极层。

公开(公告)号：US07713380B2

公开(公告)日：2010-05-11

申请号：US10765808

申请日：2004-01-27

申请人： Huang-Ming Chen ,  Chun-Li Chou ,  Chao-Cheng Chen ,  Hun-Jan Tao

发明人： Huang-Ming Chen ,  Chun-Li Chou ,  Chao-Cheng Chen ,  Hun-Jan Tao

IPC分类号： C23F1/00 ,  B23B31/28 ,  H01L21/683

CPC分类号： H01L21/68735 ,  H01J37/3244 ,  H01J37/32642 ,  H01L21/02046 ,  H01L21/31116 ,  H01L21/67069 ,  Y10S156/914 ,  Y10S156/915 ,  Y10T279/23

摘要： A method for preventing the formation of contaminating polymeric films on the backsides of semiconductor substrates includes providing an oxygen-impregnated focus ring and/or an oxygen-impregnated chuck that releases oxygen during etching operations. The method further provides delivering oxygen gas to the substrate by mixing oxygen in the cooling gas mixture, maintaining the focus ring at a temperature no greater than the substrate temperature during etching and cleaning the substrate using a two step plasma cleaning sequence that includes suspending the substrate above the chuck.

摘要翻译： 防止在半导体衬底的背面形成污染性聚合物膜的方法包括提供在蚀刻操作期间释放氧气的氧浸渍聚焦环和/或氧浸渍卡盘。 该方法还通过在冷却气体混合物中混合氧将氧气输送到衬底，在蚀刻和清洁衬底期间将聚焦环保持在不高于衬底温度的温度，使用包括悬浮衬底的两步骤等离子体清洗序列 在卡盘上方

公开(公告)号：US20080303102A1

公开(公告)日：2008-12-11

申请号：US11759791

申请日：2007-06-07

申请人： Mong-Song Liang ,  Tze-Liang Lee ,  Kuo-Tai Huang ,  Chao-Cheng Chen ,  Hao-Ming Lien ,  Chih-Tang Peng

发明人： Mong-Song Liang ,  Tze-Liang Lee ,  Kuo-Tai Huang ,  Chao-Cheng Chen ,  Hao-Ming Lien ,  Chih-Tang Peng

IPC分类号： H01L29/78

CPC分类号： H01L29/1054 ,  H01L21/76224 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846

摘要： An isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.

摘要翻译： 提供了具有局部应力源的隔离沟槽。 根据本发明的实施例，在衬底中形成沟槽并且部分地填充有电介质材料。 在一个实施例中，沟槽被填充有电介质层，并且执行平面化步骤以使其与衬底的表面平坦化。 然后将电介质材料凹入到衬底的表面下方。 在沟槽的凹陷部分中，电介质材料可以沿着侧壁保留，或者电介质材料可以沿侧壁去除。 然后可以在凹陷部分内的电介质材料上形成拉伸或压缩的应力膜。 应力膜也可以在晶体管或其它半导体结构上延伸。

公开(公告)号：US07354524B2

公开(公告)日：2008-04-08

申请号：US11358393

申请日：2006-02-21

申请人： Hui Ou Yang ,  Miao-Ju Hsu ,  Chao-Cheng Chen ,  Hun-Jan Tao

发明人： Hui Ou Yang ,  Miao-Ju Hsu ,  Chao-Cheng Chen ,  Hun-Jan Tao

IPC分类号： H01L21/00 ,  G01N21/00

CPC分类号： H01L21/31116 ,  H01J37/32935 ,  H01L22/26

摘要： A method of processing multi-layer films, the method including: (1) processing a plurality of layers according to selected parameters, (2) determining a plurality of optical characteristics each associated with one of the plurality of layers and determined during the processing of the associated one of the plurality of layers, and (3) determining dynamic processing progressions each based on one of the plurality of optical characteristics that is associated with a particular one of the plurality of layers undergoing the processing.

摘要翻译： 一种处理多层薄膜的方法，该方法包括：（1）根据选定的参数处理多个层，（2）确定多个光学特性，每个光学特性与多个层之一相关联，并在处理过程中确定 所述多个层中的相关联的一个层，以及（3）基于与经历所述处理的所述多个层中的特定一个层相关联的所述多个光学特性中的一个来确定动态处理进度。

公开(公告)号：US20050189653A1

公开(公告)日：2005-09-01

申请号：US10872946

申请日：2004-06-21

申请人： Hun-Jan Tao ,  Chao-Cheng Chen

发明人： Hun-Jan Tao ,  Chao-Cheng Chen

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L29/40

CPC分类号： H01L21/76808 ,  H01L21/76804 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： An intermediate structure from which a dual damascene structure may be fabricated includes a first-formed, unfaceted via hole and an intersecting trench both formed by gas plasma etching of a dielectric layer. The sidewall of the via hole is maintained unfaceted during and after trench formation by substantially filling it with a gas-plasma-etchable plug prior to trench formation. The presence of the plug in the via hole during gas plasma etching of the trench, also produces a trench bottom that is substantially flat.

摘要翻译： 可以制造双镶嵌结构的中间结构包括通过电介质层的气体等离子体蚀刻形成的第一形成的非平行通孔和交叉沟槽。 在沟槽形成期间和之后通孔的侧壁通过在沟槽形成之前用气体等离子体可蚀刻的塞子基本上填充而保持不通气。 在沟槽的气体等离子体蚀刻期间，插塞在通孔中的存在也产生基本上平坦的沟槽底部。