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公开(公告)号：US20060175660A1
公开(公告)日：2006-08-10
申请号：US10906238
申请日：2005-02-10
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/66666 , H01L29/78642
摘要： A vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.
摘要翻译： 提供了垂直场效应晶体管（“FET”），其包括晶体管本体区域和设置在与沟槽的侧壁相邻的衬底的绝缘体上的单晶半导体（“SOI”）区域中的源极和漏极区域。 衬底包括在SOI区域下面的掩埋绝缘体层和埋在掩埋绝缘体层下面的主体区域。 掩埋带导电地将SOI区域连接到设置在SOI区域下方的下部节点，并且主体接触从晶体管本体区域延伸到衬底的主体区域，身体接触部与掩埋带绝缘。
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公开(公告)号：US20060128055A1
公开(公告)日：2006-06-15
申请号：US10905070
申请日：2004-12-14
IPC分类号： H01L21/00
CPC分类号： H01L29/6656 , H01L29/495 , H01L29/4966 , H01L29/51 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A field effect transistor formed by a sacrificial gate process has a simplified process and improved yield by using a tunable resistant anti-reflective coating (TERA) as the cap layer over the sacrificial gate layer. The TERA layer serves as a tunable anti-reflection layer for photolithography patterning, a hardmask for etching the sacrificial gate, a polish stopping layer for planarization, and a blocking layer for preventing silicide formation over the sacrificial gate. The TERA is stripped by a two-step process that is highly selective to the nitride spacers, so that the spacers are not damaged in the process of stripping the sacrificial gate.
摘要翻译： 通过牺牲栅极工艺形成的场效应晶体管通过使用可调阻抗抗反射涂层（TERA）作为牺牲栅极层上的覆盖层，具有简化的工艺和提高的产量。 TERA层用作光刻图案的可调谐抗反射层，用于蚀刻牺牲栅极的硬掩模，用于平坦化的抛光停止层，以及用于防止在牺牲栅极上形成硅化物的阻挡层。 通过对氮化物间隔物具有高度选择性的两步法来剥离TERA，使得在剥离牺牲栅极的过程中间隔体不被损坏。
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23.发明授权公开(公告)号：US07022622B2
公开(公告)日：2006-04-04
申请号：US10710409
申请日：2004-07-08
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/0276 , C23C16/56 , H01L21/02115 , H01L21/02126 , H01L21/02274 , H01L21/02337 , H01L21/3105 , H01L21/3148 , H01L21/31633
摘要： A method for improving the properties of tunable etch resistant anti-reflective coatings (TERA) is disclosed. The method includes annealing the deposited layer of TERA in an environment containing at least one of hydrogen and deuterium. The annealed layer has an increased concentration of hydrogen and/or deuterium as compared to the deposited film, and may also have an additional concentration of hydrogen or deuterium at the interface between the substrate and the layer of TERA.
摘要翻译： 公开了一种改善可耐蚀刻抗蚀涂层（TERA）性能的方法。 该方法包括在包含氢和氘中的至少一种的环境中退火沉积的TERA层。 退火层与沉积膜相比具有增加的氢和/或氘浓度，并且还可以在衬底和TERA层之间的界面处具有额外浓度的氢或氘。
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公开(公告)号：US20050212027A1
公开(公告)日：2005-09-29
申请号：US10708861
申请日：2004-03-29
IPC分类号： H01L21/8234 , H01L21/8242 , H01L27/108 , H01L29/94
CPC分类号： H01L27/10876 , H01L27/10841 , H01L29/945 , Y10S438/931
摘要： A method of forming a trench in a semiconductor substrate includes a step of converting the cross section of the upper portion of the trench from octagonal to rectangular, so that sensitivity to alignment errors between the trench lithography and the active area lithography is reduced. Applications include a vertical transistor that becomes insensitive to misalignment between the trench and the litho for the active area, in particular a DRAM cell with a vertical transistor.
摘要翻译： 在半导体衬底中形成沟槽的方法包括将沟槽的上部的横截面从八边形转换为矩形的步骤，从而减小了沟槽光刻和有源区光刻之间对准误差的敏感性。 应用包括对于有源区域，特别是具有垂直晶体管的DRAM单元对沟槽和光刻层之间的未对准变得不敏感的垂直晶体管。
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25.发明授权Method and structure for vertical DRAM devices with self-aligned upper trench shaping 失效具有自对准上沟槽成形的垂直DRAM器件的方法和结构公开(公告)号：US06913968B2
公开(公告)日：2005-07-05
申请号：US10604565
申请日：2003-07-30
IPC分类号： H01L27/108 , H01L21/336 , H01L21/8242 , H01L27/02
CPC分类号： H01L27/10876 , H01L27/0207 , H01L27/10864 , H01L27/1087 , H01L29/945
摘要： A method and structure for a memory storage cell in a semiconductor substrate includes forming a dopant source material over a lower portion of a deep trench formed in the substrate. An upper portion of the trench is shaped to a generally rectangular configuration, and the dopant source material is annealed so as to form a buried plate of a trench capacitor. The buried plate is self aligned to the shaped upper portion of the trench.
摘要翻译： 半导体衬底中的存储单元的方法和结构包括在衬底中形成的深沟槽的下部形成掺杂剂源材料。 沟槽的上部被成形为大致矩形的构造，并且掺杂剂源材料被退火以形成沟槽电容器的掩埋板。 掩埋板与沟槽的成形上部自对准。
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公开(公告)号：US08779511B2
公开(公告)日：2014-07-15
申请号：US13530887
申请日：2012-06-22
IPC分类号： H01L27/088
CPC分类号： H01L27/1211 , H01L21/845
摘要： Thin semiconductor regions and thick semiconductor regions are formed oven an insulator layer. Thick semiconductor regions include at least one semiconductor fin. A gate conductor layer is patterned to form disposable planar gate electrodes over ETSOI regions and disposable side gate electrodes on sidewalls of semiconductor fins. End portions of the semiconductor fins are vertically recessed to provide thinned fin portions adjacent to an unthinned fin center portion. After appropriate masking by dielectric layers, selective epitaxy is performed on planar source and drain regions of ETSOI field effect transistors (FETs) to form raised source and drain regions. Further, fin source and drain regions are grown on the thinned fin portions. Source and drain regions, fins, and the disposable gate electrodes are planarized. The disposable gate electrodes are replaced with metal gate electrodes. FinFETs and ETSOI FETs are provided on the same semiconductor substrate.
摘要翻译： 薄半导体区域和厚半导体区域被形成为绝缘体层。 厚半导体区域包括至少一个半导体鳍片。 图案化栅极导体层以在半导体鳍片的侧壁上的ETSOI区域和一次侧栅电极上形成一次性平面栅电极。 半导体翅片的端部垂直凹入，以提供与未固定的翅片中心部分相邻的变薄的翅片部分。 在通过介电层适当掩蔽之后，在ETSOI场效应晶体管（FET）的平面源极和漏极区域上进行选择性外延以形成升高的源极和漏极区域。 此外，翅片源极和漏极区域在薄的鳍部上生长。 源极和漏极区域，鳍片和一次性栅电极被平坦化。 一次性栅电极被金属栅电极代替。 FinFET和ETSOI FET设置在相同的半导体衬底上。
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27.发明申请METHODS OF FABRICATING P-I-N DIODES, STRUCTURES FOR P-I-N DIODES AND DESIGN STRUCTURE FOR P-I-N DIODES 有权制备P-I-N二极体的方法，P-I-N二极体的结构和P-I-N二极体的设计结构公开(公告)号：US20100173449A1
公开(公告)日：2010-07-08
申请号：US12349018
申请日：2009-01-06
CPC分类号： H01L29/868 , H01L29/6609
摘要： Methods of fabricating P-I-N diodes, structures for P-I-N diodes and design structure for P-I-N diodes. A method includes: forming a trench in a silicon substrate; forming a doped region in the substrate abutting the trench; growing an intrinsic epitaxial silicon layer on surfaces of the trench; depositing a doped polysilicon layer to fill remaining space in the trench, performing a chemical mechanical polish so top surfaces of the intrinsic epitaxial silicon layer and the doped polysilicon layer are coplanar; forming a dielectric isolation layer in the substrate; forming a dielectric layer on top of the isolation layer; and forming a first metal contact to the doped polysilicon layer through the dielectric layer and a second contact to the doped region the dielectric and through the isolation layer.
摘要翻译： 制造P-I-N二极管的方法，P-I-N二极管的结构和P-I-N二极管的设计结构。 一种方法包括：在硅衬底中形成沟槽; 在所述衬底中形成邻接所述沟槽的掺杂区域; 在沟槽的表面上生长本征的外延硅层; 沉积掺杂多晶硅层以填充沟槽中的剩余空间，执行化学机械抛光，使得本征外延硅层和掺杂多晶硅层的顶表面是共面的; 在衬底中形成绝缘隔离层; 在隔离层的顶部形成介电层; 以及通过介电层形成第一金属接触到掺杂多晶硅层，以及通过第二接触到掺杂区域介电层并通过隔离层。
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28.发明授权Method of making a FinFET device structure having dual metal and high-k gates 失效制造具有双金属和高k栅极的FinFET器件结构的方法公开(公告)号：US07736965B2
公开(公告)日：2010-06-15
申请号：US11951552
申请日：2007-12-06
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L27/1211 , H01L29/517 , H01L29/66795
摘要： Methods include making a FinFET device structure having multiple FinFET devices (e.g. ntype and/or ptype) with different metal conductors and/or different high-k insulators in the gates formed on a SOI substrate. One such method includes removing a second semiconductor layer from a second metal layer in a region above a second cap layer, from adjoining regions and from regions adjacent to a second fin.
摘要翻译： 方法包括在SOI衬底上形成的栅极中制造具有多个FinFET器件（例如n型和/或p型）的FinFET器件结构，其具有不同的金属导体和/或不同的高k绝缘体。 一种这样的方法包括从邻接的区域和邻近第二鳍片的区域的第二盖层上方的区域中的第二金属层去除第二半导体层。
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公开(公告)号：US07682859B2
公开(公告)日：2010-03-23
申请号：US11931836
申请日：2007-10-31
IPC分类号： H01L21/00
CPC分类号： H01L29/1054 , H01L21/823412 , H01L29/739 , H01L29/78687
摘要： A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and forming a non-strained device in the relaxed material is disclosed. In one embodiment, the strained material is silicon (Si) in either a tensile or compressive state, and the relaxed material is Si in a normal state. A buffer layer of silicon germanium (SiGe), silicon carbon (SiC), or similar material is formed on the substrate and has a lattice constant/structure mis-match with the substrate. A relaxed layer of SiGe, SiC, or similar material is formed on the buffer layer and places the strained material in the tensile or compressive state. In another embodiment, carbon-doped silicon or germanium-doped silicon is used to form the strained material. The structure includes a multi-layered substrate having strained and non-strained materials patterned thereon.
摘要翻译： 一种包括在基板上形成应变材料和松弛材料的图案的方法; 在应变材料中形成应变装置; 并且公开了在松弛材料中形成非应变装置。 在一个实施例中，应变材料是处于拉伸或压缩状态的硅（Si），松弛材料是处于正常状态的Si。 在衬底上形成硅锗（SiGe），硅碳（SiC）或类似材料的缓冲层，其晶格常数/结构与衬底失配。 在缓冲层上形成SiGe，SiC或类似材料的松散层，并将应变材料置于拉伸或压缩状态。 在另一个实施例中，使用掺碳硅或锗掺杂硅来形成应变材料。 该结构包括具有图案化的应变和非应变材料的多层基底。
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公开(公告)号：US07615816B2
公开(公告)日：2009-11-10
申请号：US11692473
申请日：2007-03-28
IPC分类号： H01L27/108
CPC分类号： H01L27/10876 , H01L27/0207 , H01L27/10864 , H01L27/1087 , H01L29/945
摘要： A buried plate region for a semiconductor memory storage capacitor is self aligned with respect to an upper portion of a deep trench containing the memory storage capacitor.
摘要翻译： 用于半导体存储器存储电容器的掩埋板区域相对于包含存储器存储电容器的深沟槽的上部自对准。
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