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    Methods for forming anti-reflection structures for CMOS image sensors
    21.
    发明授权
    Methods for forming anti-reflection structures for CMOS image sensors 有权
    CMOS图像传感器形成抗反射结构的方法

    公开(公告)号：US08409904B2

    公开(公告)日：2013-04-02

    申请号：US13165375

    申请日：2011-06-21

    申请人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Charles F. Musante

    发明人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Charles F. Musante

    IPC分类号： H01L21/00

    CPC分类号： H01L27/14685 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14645 ,  H01L27/14689 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

    摘要： Protuberances, having vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode, are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-assembling block copolymers that form an array of sublithographic features of a first polymeric block component within a matrix of a second polymeric block component. The pattern of the polymeric block component is transferred into a first optical layer to form an array of nanoscale protuberances. Alternately, conventional lithography may be employed to form protuberances having dimensions less than the wavelength of light. A second optical layer is formed directly on the protuberances of the first optical layer. The interface between the first and second optical layers has a graded refractive index, and provides high transmission of light with little reflection.

    摘要翻译： 在具有不同折射率的两层之间的光学界面处形成具有小于由光电二极管可检测的光的波长范围的垂直和横向尺寸的突起。 突起可以通过采用在第二聚合物嵌段组分的基质内形成第一聚合物嵌段组分的亚光刻特征阵列的自组装嵌段共聚物来形成。 聚合物嵌段组分的图案被转移到第一光学层中以形成纳米级突起的阵列。 或者，可以使用常规光刻来形成尺寸小于光的波长的突起。 第二光学层直接形成在第一光学层的突起上。 第一和第二光学层之间的界面具有渐变的折射率，并提供很少的反射光的高透射率。

    USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES
    23.
    发明申请
    USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES 有权
    使用联系人创建设备上的差别应力

    公开(公告)号：US20120074502A1

    公开(公告)日：2012-03-29

    申请号：US12892474

    申请日：2010-09-28

    申请人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Robert R. Robison

    发明人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Robert R. Robison

    IPC分类号： H01L25/11 ,  H01L21/77

    CPC分类号： H01L21/823807 ,  H01L21/28518 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). One embodiment of this invention includes creating this differential stress by varying the deposition conditions for forming PFET and NFET contacts, for example, the temperature at which the fill materials are deposited, and the rate at which the fill materials are deposited. In another embodiment, the differential stress is created by filling the contacts with differing materials that will impart differential stress due to differing coefficient of thermal expansions. In another embodiment, the differential stress is created by including a silicide layer within the NFET contacts and/or the PFET contacts.

    摘要翻译： 这里公开了使用触点在集成电路（IC）芯片中的器件上产生差分应力的各种方法和结构。 公开了具有p型场效应晶体管（PFET）和n型场效应晶体管（NFET）的IC芯片。 本发明的一个实施例包括通过改变用于形成PFET和NFET触点的沉积条件（例如，沉积填充材料的温度）以及填充材料沉积的速率来产生该微分应力。 在另一个实施例中，通过用不同的材料填充触点来产生差分应力，这些材料将由于不同的热膨胀系数而赋予差压。 在另一个实施例中，通过在NFET触点和/或PFET触点内包括硅化物层来产生差分应力。

    Method and structure for charge dissipation during fabrication of integrated circuits and isolation thereof
    24.
    发明授权
    Method and structure for charge dissipation during fabrication of integrated circuits and isolation thereof 有权
    集成电路制造期间电荷耗散的方法和结构及其分离

    公开(公告)号：US07445966B2

    公开(公告)日：2008-11-04

    申请号：US11160468

    申请日：2005-06-24

    申请人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Timothy D. Sullivan ,  Steven H. Voldman

    发明人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Timothy D. Sullivan ,  Steven H. Voldman

    IPC分类号： H01L23/60

    CPC分类号： H01L27/0248 ,  Y10S438/926

    摘要： A method, structure and design method for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.

    摘要翻译： 一种用于在集成电路制造期间耗散电荷的方法，结构和设计方法。 该结构包括：衬底中的衬底接触; 衬底上的一个或多个布线层; 一个或多个导电电荷耗散结构，其从所述一个或多个布线层的最上层布线层的顶表面延伸通过所述一个或多个布线层的每个下布线层与所述基板接触电接触; 以及在基板中和在一个或多个布线层中的电路结构，电荷耗散结构在电路结构之间分散的一个或多个电荷耗散结构不会电接触任何一个或多个布线层中的任何一个电路结构。

    Fuse for three dimensional solid-state battery
    26.
    发明授权
    Fuse for three dimensional solid-state battery 有权
    保险丝三维固态电池

    公开(公告)号：US08835029B2

    公开(公告)日：2014-09-16

    申请号：US13252366

    申请日：2011-10-04

    申请人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

    发明人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

    IPC分类号： H01M6/40 ,  H01M10/04 ,  H01M10/42

    CPC分类号： H01M10/04 ,  H01M2/204 ,  H01M2/24 ,  H01M2/34 ,  H01M4/767 ,  H01M10/02 ,  H01M10/052 ,  H01M10/0562 ,  H01M10/42 ,  Y02E60/12 ,  Y10T29/49108

    摘要： A solid-state battery structure having a plurality of battery cells formed in a substrate, method of manufacturing the same and design structure thereof are provided. The battery structure includes a patterned cathode electrode layer formed upon the substrate and structured to form a plurality of sub-arrays of the battery cells. The battery structure further includes a plurality of fuse wires structured to interconnect at least two adjacent sub-arrays. At least one of the plurality of fuse wires is structured to be blown to disconnect an interconnection having a defective sub-array. Advantageously, the plurality of fuse wires is an integral part of the battery structure.

    摘要翻译： 提供了具有形成在基板中的多个电池单元的固态电池结构，其制造方法和设计结构。 电池结构包括形成在基板上并构造成形成电池单元的多个子阵列的图案化阴极电极层。 电池结构还包括构造成互连至少两个相邻子阵列的多个熔丝。 多个熔丝中的至少一个被构造成被吹塑以断开具有缺陷子阵列的互连。 有利的是，多个熔丝是电池结构的组成部分。

    USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES
    27.
    发明申请
    USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES 有权
    使用联系人创建设备上的差别应力

    公开(公告)号：US20120074501A1

    公开(公告)日：2012-03-29

    申请号：US12892465

    申请日：2010-09-28

    申请人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Robert R. Robison

    发明人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Robert R. Robison

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/76879 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092

    摘要： Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET.

    摘要翻译： 这里公开了使用触点在集成电路（IC）芯片中的器件上产生差分应力的各种方法和结构。 公开了具有p型场效应晶体管（PFET）和n型场效应晶体管（NFET）的IC芯片，与PFET的源极/漏极区域的PFET接触以及与源极/漏极区域的NFET接触 的NFET。 在第一实施例中，在PFET接触和PFET的源极/漏极区之间仅包含PFET接触下的硅锗（SiGe）层。 在第二实施例中，PFET触点延伸到PFET的源极/漏极区域中，或者NFET触点延伸到NFET的源极/漏极区域。

    Semiconductor wafer processing method that allows device regions to be selectively annealed following back end of the line (BEOL) metal wiring layer formation
    28.
    发明授权
    Semiconductor wafer processing method that allows device regions to be selectively annealed following back end of the line (BEOL) metal wiring layer formation 有权
    半导体晶片处理方法允许器件区域在线后面（BEOL）金属布线层形成之后被选择性地退火

    公开(公告)号：US08021950B1

    公开(公告)日：2011-09-20

    申请号：US12911940

    申请日：2010-10-26

    申请人： Wagdi W. Abadeer ,  Lilian Kamal, legal representative ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Tom C. Lee

    发明人： Wagdi W. Abadeer ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Tom C. Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28044 ,  H01L21/268 ,  H01L29/1054 ,  H01L29/4925 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

    摘要： Disclosed are embodiments of a semiconductor wafer processing method that allow device regions to be selectively annealed following back end of the line (BEOL) metal wiring formation without degrading wiring layer reliability. In the embodiments, a semiconductor device is formed adjacent to the top surface of a wafer such that it incorporates a selectively placed infrared absorbing layer (IAL). Then, following BEOL metal wiring formation, the bottom surface of the wafer is exposed to an infrared light having a wavelength that is transparent to the wafer. The infrared light is absorbed by and, thereby heats up the IAL to a first predetermined temperature (e.g., a dopant activation temperature, a temperature required for a state change, etc.). The resulting heat is transferred from the IAL to an adjacent region of the semiconductor device without raising the temperature of the metal wiring above a second predetermined temperature (e.g., a temperature that could degrade the metal wiring) that is lower than the first predetermined temperature.

    摘要翻译： 公开了允许器件区域在线路后端（BEOL）金属布线形成之后选择性退火的半导体晶片处理方法的实施例，而不会降低布线层的可靠性。 在实施例中，半导体器件形成为与晶片的顶表面相邻，使得其结合有选择放置的红外线吸收层（IAL）。 然后，在BEOL金属布线形成之后，晶片的底面暴露于对晶片透明的波长的红外光。 红外光被IAL吸收，从而将IAL加热到第一预定温度（例如，掺杂剂活化温度，状态改变所需的温度等）。 所产生的热量从IAL转移到半导体器件的相邻区域，而不会将金属布线的温度升高到低于第一预定温度的第二预定温度（例如，可能降低金属布线的温度）。