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公开(公告)号：US10957392B2
公开(公告)日：2021-03-23
申请号：US16233404
申请日：2018-12-27
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Feng-Min Lee , Yu-Yu Lin
IPC: G11C16/04 , G11C16/08 , H01L29/792 , H01L29/788 , G11C16/26 , G06N3/063 , G06F7/544 , G11C16/10 , G11C11/54 , G06F7/38 , H01L27/1157 , H01L27/11556 , H01L27/11582 , H01L27/11524
Abstract: An array of variable resistance cells based on a programmable threshold transistor and a resistor connected in parallel is described, including 3D and split gate variations. An input voltage applied to the transistor, and the programmable threshold of the transistor, can represent variables of sum-of-products operations. Programmable threshold transistors in the variable resistance cells comprise charge trapping memory transistors, such as floating gate transistors or dielectric charge trapping transistors. The resistor in the variable resistance cells can comprise a buried implant resistor connecting the current-carrying terminals (e.g. source and drain) of the programmable threshold transistor. A voltage sensing sense amplifier is configured to sense the voltage generated by the variable resistance cells as a function of an applied current and the resistance of the variable resistance cells.
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公开(公告)号：US10476002B2
公开(公告)日：2019-11-12
申请号：US15690353
申请日：2017-08-30
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu Lin , Feng-Min Lee , Po-Hao Tseng , Kai-Chieh Hsu
Abstract: A method for treating a semiconductor structure comprising memory devices is provided, wherein a forming process is conducted to initialize operation of the memory devices. The semiconductor structure is subjected to a forming thermal treatment, and step of saving data to the memory devices is performed after the forming thermal treatment.
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公开(公告)号：US20190138881A1
公开(公告)日：2019-05-09
申请号：US15803971
申请日：2017-11-06
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu Lin , Feng-Min Lee
IPC: G06N3/04
Abstract: A neuromorphic computing system includes a synapse array, a switching circuit, a sensing circuit and a processing circuit. The synapse array includes row lines, column lines and synapses. The processing circuit is coupled to the switching circuit and the sensing circuit and is configured to connect a particular column line in the column lines to the first terminal by using the switching circuit, obtain a first voltage value from the particular column line by using the sensing circuit when the particular line is connected to the first terminal, connect the particular column line to the second terminal by using the switching circuit, obtain a second voltage value from the particular column line by using the sensing circuit when the particular line is connected to the second terminal, and estimate a sum-of-product sensing value according to a voltage difference between the first voltage value and the second voltage value.
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24.发明授权公开(公告)号：US09852791B1
公开(公告)日：2017-12-26
申请号：US15487458
申请日：2017-04-14
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Po-Hao Tseng , Ming-Hsiu Lee , Kai-Chieh Hsu , Yu-Yu Lin , Feng-Min Lee
CPC classification number: G11C13/0059 , G06F21/70 , G06F21/73 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C29/023 , G11C29/028 , G11C2013/0083 , G11C2013/0092 , H01L21/02 , H01L29/18 , H01L45/00 , H01L45/06 , H04L9/0866 , H04L9/3278
Abstract: A semiconductor memory device includes programmable resistance memory cells and a controller which applies a forming pulse to first and second groups of the programmable resistance memory cells for inducing a change in the first group from an initial resistance range to an intermediate resistance range, and for inducing the second group having a resistance outside the intermediate range. When a forming rate is lower than a first forming threshold rate, the controller adjusts the forming pulse until the forming rate is higher than the first forming threshold rate. When a forming rate is higher than the first forming threshold rate but lower than a second forming threshold rate, the controller adjusts the forming pulse until the forming rate is higher than the second forming threshold rate. The controller applies a programming pulse to the first and second groups and generates a chip ID of the semiconductor memory device.
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公开(公告)号：US09515258B2
公开(公告)日：2016-12-06
申请号：US14729181
申请日：2015-06-03
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu Lin , Feng-Min Lee , Chien-Hung Lu , Chin-Yi Tseng
IPC: H01L45/00
CPC classification number: H01L45/1253 , H01L45/04 , H01L45/1233 , H01L45/1246 , H01L45/146 , H01L45/16 , H01L45/1633 , H01L45/1683
Abstract: A memory structure including an insulating layer, a first electrode layer and a first barrier is provided. The insulating layer has a recess. The first electrode layer is formed in the recess and has a first top surface. The first barrier is formed between the insulating layer and the first electrode layer, and has a second top surface lower than the first top surface. The first top surface and the second top surface are lower than an opening of the recess.
Abstract translation: 提供了包括绝缘层，第一电极层和第一屏障的存储结构。 绝缘层具有凹部。 第一电极层形成在凹部中并且具有第一顶表面。 第一阻挡层形成在绝缘层和第一电极层之间，并且具有比第一顶表面低的第二顶表面。 第一顶表面和第二顶表面比凹口的开口低。
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Patent Agency Ranking
公开(公告)号：US09514815B1
公开(公告)日：2016-12-06
申请号：US14877740
申请日：2015-10-07
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu Lin , Feng-Min Lee
CPC classification number: G11C13/0069 , G11C13/0007 , G11C13/0064 , G11C13/0097 , G11C2013/0073
Abstract: Circuitry coupled to a programmable element comprising metal oxide is configured to execute a program-verify operation including: an initial cycle of a program operation and a verify operation, and subsequent cycles. The initial cycle includes an initial instance of the program operation to establish a cell resistance of the programmable element, and an initial instance of the verify operation to determine whether the cell resistance of the memory cell is within the target resistance range. At least one of the subsequent cycles includes an additional pulse having a second polarity to the programmable element, and a subsequent instance of the verify operation. The first polarity of the initial program pulse and the second polarity of the additional pulse have opposite polarities. A subsequent instance of the program operation includes applying a subsequent program pulse having the first polarity to the programmable element.
Abstract translation: 耦合到包括金属氧化物的可编程元件的电路被配置为执行程序验证操作，包括：程序操作和验证操作的初始循环以及随后的循环。 初始周期包括用于建立可编程元件的单元电阻的程序操作的初始实例，以及用于确定存储器单元的单元电阻是否在目标电阻范围内的验证操作的初始实例。 后续周期中的至少一个包括对可编程元件具有第二极性的附加脉冲以及验证操作的后续实例。 初始编程脉冲的第一极性和附加脉冲的第二极性具有相反的极性。 随后的程序操作实例包括将具有第一极性的后续编程脉冲施加到可编程元件。
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公开(公告)号：US09466792B2
公开(公告)日：2016-10-11
申请号：US14623654
申请日：2015-02-17
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu Lin , Feng-Min Lee
IPC: H01L45/00
CPC classification number: H01L45/124 , H01L45/04 , H01L45/08 , H01L45/1233 , H01L45/1246 , H01L45/146 , H01L45/1616 , H01L45/1633
Abstract: A memory device comprises a substrate, a first electrode layer, a spacer, a memory layer and a second electrode layer. The substrate has a recess. The first electrode layer is formed in the recess and has a top surface exposed from an opening of the recess. The spacer covers on a portion of the top surface, so as to define a contact area on the top surface. The memory layer is formed on the contact area. The second electrode layer is formed on the memory layer and electrically connected to the memory layer.
Abstract translation: 存储器件包括衬底，第一电极层，间隔物，存储层和第二电极层。 衬底具有凹部。 第一电极层形成在凹部中并且具有从凹部的开口露出的顶表面。 间隔件覆盖在顶表面的一部分上，以便限定顶表面上的接触区域。 存储层形成在接触区域上。 第二电极层形成在存储层上并与存储层电连接。
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28.发明授权公开(公告)号：US08987699B2
公开(公告)日：2015-03-24
申请号：US13871040
申请日：2013-04-26
Applicant: Macronix International Co., Ltd.
Inventor： Feng-Min Lee , Yu-Yu Lin , Wei-Chih Chien , Wei-Chen Chen , Ming-Hsiu Lee
IPC: H01L29/66 , H01L45/00 , H01L29/861 , E04H17/16
CPC classification number: H01L29/66969 , E04H17/16 , H01L27/249 , H01L29/8615 , H01L45/08 , H01L45/085 , H01L45/12 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/1266 , H01L45/145 , H01L45/146 , H01L45/1608 , H01L45/1633
Abstract: A conductive bridge resistive memory device is provided, comprising a first electrode, a memory layer electrically coupled to the first electrode, an ion-supplying layer containing a source of ions of a first metal element capable of diffusion into and out of the memory layer, a semiconductor layer disposed between the memory layer and the ion-supplying layer, and a second electrode electrically coupled to the ion-supplying layer.
Abstract translation: 提供了一种导电桥电阻性存储器件，包括第一电极，电耦合到第一电极的存储层，含有能够扩散进出存储层的第一金属元素的离子源的离子供给层， 设置在所述存储层和所述离子供给层之间的半导体层以及与所述离子供给层电耦合的第二电极。
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公开(公告)号：US08962466B2
公开(公告)日：2015-02-24
申请号：US13895059
申请日：2013-05-15
Applicant: Macronix International Co., Ltd.
Inventor： Feng-Min Lee , Erh-Kun Lai , Wei-Chih Chien , Ming-Hsiu Lee , Chih-Chieh Yu
IPC: H01L29/02 , H01L21/3205 , H01L47/00 , H01L21/02 , H01L45/00
CPC classification number: H01L21/02551 , H01L21/02554 , H01L21/02565 , H01L21/02614 , H01L27/2436 , H01L45/085 , H01L45/1233 , H01L45/141 , H01L45/146 , H01L45/1633
Abstract: A metal oxide formed by in situ oxidation assisted by radiation induced photo-acid is described. The method includes depositing a photosensitive material over a metal surface of an electrode. Upon exposure to radiation (for example ultraviolet light), a component, such as a photo-acid generator, of the photosensitive material forms an oxidizing reactant, such as a photo acid, which causes oxidation of the metal at the metal surface. As a result of the oxidation, a layer of metal oxide is formed. The photosensitive material can then be removed, and subsequent elements of the component can be formed in contact with the metal oxide layer. The metal oxide can be a transition metal oxide by oxidation of a transition metal. The metal oxide layer can be applied as a memory element in a programmable resistance memory cell. The metal oxide can be an element of a programmable metallization cell.
Abstract translation: 描述了通过由辐射诱导的光酸辅助的原位氧化形成的金属氧化物。 该方法包括将感光材料沉积在电极的金属表面上。 感光材料暴露于辐射（例如紫外光）时，诸如光酸产生剂的组分形成氧化反应物，例如导致金属在金属表面氧化的光酸。 作为氧化的结果，形成金属氧化物层。 然后可以去除感光材料，并且可以将元件的后续元件形成为与金属氧化物层接触。 金属氧化物可以通过过渡金属的氧化而成为过渡金属氧化物。 金属氧化物层可以作为可编程电阻存储单元中的存储元件来应用。 金属氧化物可以是可编程金属化电池的元件。
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30.发明申请公开(公告)号：US20140203235A1
公开(公告)日：2014-07-24
申请号：US13871040
申请日：2013-04-26
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Feng-Min Lee , Yu-Yu Lin , Wei-Chih Chien , Wei-Chen Chen , Ming-Hsiu Lee
IPC: H01L29/861 , H01L29/66
CPC classification number: H01L29/66969 , E04H17/16 , H01L27/249 , H01L29/8615 , H01L45/08 , H01L45/085 , H01L45/12 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/1266 , H01L45/145 , H01L45/146 , H01L45/1608 , H01L45/1633
Abstract: A conductive bridge resistive memory device is provided, comprising a first electrode, a memory layer electrically coupled to the first electrode, an ion-supplying layer containing a source of ions of a first metal element capable of diffusion into and out of the memory layer, a semiconductor layer disposed between the memory layer and the ion-supplying layer, and a second electrode electrically coupled to the ion-supplying layer.
Abstract translation: 提供了一种导电桥电阻性存储器件，包括第一电极，电耦合到第一电极的存储层，含有能够扩散进出存储层的第一金属元素的离子源的离子供给层， 设置在所述存储层和所述离子供给层之间的半导体层以及与所述离子供给层电耦合的第二电极。
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