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    MEMORY WITH PARTIAL BANK REFRESH
    21.
    发明申请
    MEMORY WITH PARTIAL BANK REFRESH 有权

    公开(公告)号：US20210295901A1

    公开(公告)日：2021-09-23

    申请号：US17338191

    申请日：2021-06-03

    Applicant: Micron Technology, Inc.

    Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

    IPC: G11C11/406 ,  G11C29/00 ,  G11C11/409 ,  G11C11/4074

    Abstract: Memory with partial bank refresh is disclosed herein. In one embodiment, a memory system includes a memory controller and a memory device operably connected to the memory controller. The memory device includes (i) a memory array having a memory bank with a plurality of memory cells arranged in a plurality of memory rows and (ii) circuitry. In some embodiments, the circuitry is configured to disable at least one memory row of the memory bank from receiving refresh commands such that memory cells of the at least one memory row are not refreshed during refresh operations of the memory device. In some embodiments, the memory controller is configured to track memory rows that include utilized memory cells and/or to write data to the memory rows in accordance with a programming sequence of the memory device.

    Phase charge sharing
    22.
    发明授权
    Phase charge sharing 有权

    公开(公告)号：US11087829B2

    公开(公告)日：2021-08-10

    申请号：US16926476

    申请日：2020-07-10

    Applicant: Micron Technology, Inc.

    Inventor： James S. Rehmeyer ,  George B. Raad ,  Debra M. Bell ,  Markus H. Geiger ,  Anthony D. Veches

    IPC: G11C11/4094 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/406

    Abstract: Methods, systems, and devices for phase charge sharing are described. In some memory systems or memory devices, one or more decoders may be used to bias access lines of a memory die. The decoders may transfer voltage or current between a first conductive line of the decoder and a second conductive line of the decoder via a shorting device. Transferring the voltage or current may be performed as part of or in association with an operation (e.g., an activate or pre-charge operation) to access one or more memory cells of the memory die. In some examples, the decoders may transfer voltage or current between a first conductive line of a decoder associated with a first refresh activity and a second conductive line of the decoder associated with a second refresh activity via a shorting device.

    SEMICONDUCTOR DEVICE WITH USER DEFINED OPERATIONS AND ASSOCIATED METHODS AND SYSTEMS
    23.
    发明申请
    SEMICONDUCTOR DEVICE WITH USER DEFINED OPERATIONS AND ASSOCIATED METHODS AND SYSTEMS 有权

    公开(公告)号：US20210216397A1

    公开(公告)日：2021-07-15

    申请号：US17214684

    申请日：2021-03-26

    Applicant: Micron Technology, Inc.

    Inventor： Anthony D. Veches

    IPC: G06F11/10

    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a memory device may select an option for a host device to access a memory array including a first portion configured to store user data and a second portion configured to store different data based on whether an ECC function of the memory device is enabled or disabled—e.g., storing ECC data when the ECC function is enabled, storing additional user data, metadata, or both when the ECC function is disabled. The host device may disable the ECC function and transmit an input to the memory device as to how to access the memory array. The memory device, based on the input, may select the option for the host device to access the memory array and communicate with the host device in accordance with the selected option.

    Memory with on-die data transfer
    24.
    发明授权
    Memory with on-die data transfer 有权

    公开(公告)号：US11024367B2

    公开(公告)日：2021-06-01

    申请号：US17017545

    申请日：2020-09-10

    Applicant: Micron Technology, Inc.

    Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

    IPC: G11C5/02 ,  G11C11/4093 ,  G11C11/406 ,  G11C7/18 ,  H01L25/10 ,  G11C11/4096

    Abstract: Memory devices and systems with on-die data transfer capability, and associated methods, are disclosed herein. In one embodiment, a memory device includes an array of memory cells and a plurality of input/output lines operably connecting the array to data pads of the device. In some embodiments, the memory device can further include a global cache and/or a local cache. The memory device can be configured to internally transfer data stored at a first location in the array to a second location in the array without outputting the data from the memory device. To transfer the data, the memory device can copy data on one row of memory cells to another row of memory cells, directly write data to the second location from the first location using data read/write lines of the input/output lines, and/or read the data into and out of the global cache and/or the local cache.

    Semiconductor device with user defined operations and associated methods and systems
    25.
    发明授权
    Semiconductor device with user defined operations and associated methods and systems 有权

    公开(公告)号：US10963336B2

    公开(公告)日：2021-03-30

    申请号：US16554958

    申请日：2019-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Anthony D. Veches

    IPC: G06F11/10

    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a memory device may select an option for a host device to access a memory array including a first portion configured to store user data and a second portion configured to store different data based on whether an ECC function of the memory device is enabled or disabled—e.g., storing ECC data when the ECC function is enabled, storing additional user data, metadata, or both when the ECC function is disabled. The host device may disable the ECC function and transmit an input to the memory device as to how to access the memory array. The memory device, based on the input, may select the option for the host device to access the memory array and communicate with the host device in accordance with the selected option.

    Refresh-related activation in memory
    26.
    发明授权
    Refresh-related activation in memory 有权

    公开(公告)号：US10910033B2

    公开(公告)日：2021-02-02

    申请号：US16220742

    申请日：2018-12-14

    Applicant: Micron Technology, Inc.

    Inventor： Stephen Michael Kaminski ,  Anthony D. Veches ,  James S. Rehmeyer ,  Debra M. Bell ,  Dale Herber Hiscock ,  Joshua E. Alzheimer

    IPC: G11C11/406 ,  G11C11/4072 ,  G11C11/4091

    Abstract: Methods, systems, and devices for refresh-related activation in memory are described. A memory device may conduct a refresh operation to preserve the integrity of data. A refresh operation may be associated with a refresh time where the memory device is unable to execute or issue any commands (e.g., access commands). By posting (e.g., saving) one or more commands and/or row addresses during the refresh time, the memory device may be configured to execute the saved commands and/or re-open one or more rows associated with the saved row addresses at a later time (e.g., upon completion of the refresh operation). Accordingly, fewer commands may be issued to activate the memory cells after the refresh time.

    Methods and systems for improving power delivery and signaling in stacked semiconductor devices
    27.
    发明授权
    Methods and systems for improving power delivery and signaling in stacked semiconductor devices 有权

    公开(公告)号：US10304809B2

    公开(公告)日：2019-05-28

    申请号：US16115492

    申请日：2018-08-28

    Applicant: Micron Technology, Inc.

    Inventor： Anthony D. Veches

    IPC: H01L23/48 ,  H01L25/065 ,  H01L25/00 ,  H01L23/64

    Abstract: Semiconductor die assemblies including stacked semiconductor dies having parallel plate capacitors formed between adjacent pairs of semiconductor dies in the stack, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die and a second semiconductor die stacked over the first semiconductor die. The first semiconductor die includes an upper surface having a first capacitor plate formed thereon, and the second semiconductor die includes a lower surface facing the upper surface of the first semiconductor die and having a second capacitor plate formed thereon. A dielectric material is formed at least partially between the first and second capacitor plates. The first capacitor plate, second capacitor plate, and dielectric material together form a capacitor that stores charge locally within the stack, and that can be accessed by the first and/or second semiconductor dies.

    APPARATUSES AND METHODS FOR UNIT IDENTIFICATION IN A MASTER/SLAVE MEMORY STACK
    28.
    发明申请
    APPARATUSES AND METHODS FOR UNIT IDENTIFICATION IN A MASTER/SLAVE MEMORY STACK 有权
    在主/从存储堆栈中进行单元识别的装置和方法

    公开(公告)号：US20140347948A1

    公开(公告)日：2014-11-27

    申请号：US14455456

    申请日：2014-08-08

    Applicant: Micron Technology, Inc.

    Inventor： Anthony D. Veches ,  Joshua E. Alzheimer ,  Dennis R. Blankenship

    IPC: G11C8/12

    CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/14 ,  G11C7/00 ,  G11C7/10

    Abstract: Apparatuses and methods including a plurality of memory units are disclosed. An example apparatus includes a plurality of memory units. Each of the plurality of memory units include a master/slave identification (ID) node coupled to a first voltage source node via a resistive element. Each of the plurality of memory units further include a master/slave ID circuit configured to determine whether a memory unit is a master memory unit or a slave memory unit based on a voltage level detected at the master/slave ID node. The master/slave ID node of each of the plurality of memory units other than a first memory unit is further coupled to a respective second voltage source node via a through—substrate via (TSV) of a respective adjacent memory unit of the plurality of memory units.

    Abstract translation: 公开了包括多个存储单元的装置和方法。 示例性装置包括多个存储单元。 多个存储单元中的每一个包括经由电阻元件耦合到第一电压源节点的主/从标识（ID）节点。 多个存储单元中的每一个还包括主/从ID电路，其被配置为基于在主/从ID节点处检测到的电压电平来确定存储器单元是主存储器单元还是从存储器单元。 除了第一存储器单元之外的多个存储器单元中的每一个的主/从ID节点还经由穿过基板经由多个存储器中的相应相邻存储器单元的（TSV）耦合到相应的第二电压源节点 单位。

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