公开(公告)号：US12079509B2

公开(公告)日：2024-09-03

申请号：US17868286

申请日：2022-07-19

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Daniele Balluchi ,  Paolo Amato ,  Danilo Caraccio ,  Marco Sforzin

IPC: G06F3/06 ,  G06F3/00 ,  G06F11/00 ,  G06F11/10

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F11/1048

Abstract: A memory controller can include media controllers respectively coupled to memory devices. A first set of media controllers can be enabled during a first operating mode of the memory controller and a second set of media controller can be enabled during a second operating mode of the memory controller, during which some features, such as low-power features, can be disabled. Data accessed by each media controller of the first set can be aligned prior to being further transmitted to other circuitries of the memory controller that are dedicated, for example, for the low-power features.

公开(公告)号：US20230418756A1

公开(公告)日：2023-12-28

申请号：US18215117

申请日：2023-06-27

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Patrick Estep ,  Stephen S. Pawlowski ,  Nicola Del Gatto

IPC: G06F12/0888 ,  G06F12/0804

CPC classification number: G06F12/0888 ,  G06F12/0804

Abstract: Systems, apparatuses, and methods related to a memory controller for cache bypass are described. An example memory controller can be coupled to a memory device. The example memory controller can include a cache including a cache sequence controller configured to determine a quantity of a given type of result of cache look-up operations, determine the quantity satisfies a bypass threshold, and cause performance of a bypass memory operation that bypasses the cache and accesses the memory device.

公开(公告)号：US20230214323A1

公开(公告)日：2023-07-06

申请号：US17973867

申请日：2022-10-26

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri

IPC: G06F12/0804

CPC classification number: G06F12/0804 ,  G06F2212/1024

Abstract: Systems, apparatuses, and methods related to selectable cache writing policies for cache management are described. A cache writing policy to manage a cache can be selected among cache writing policies based on a number of tracked criteria, which can provide cache management with a particular cache writing policy that will likely incur less latency than the other policies.

公开(公告)号：US20230062130A1

公开(公告)日：2023-03-02

申请号：US17895041

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： Simone Corbetta ,  Antonino Caprì ,  Emanuele Confalonieri

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods related to access request management using sub-commands. Access requests received from a host system can be managed using a respective set of sub-commands corresponding to each access request and whose status can be tracked. Tracking how far access requests are processed at a fine granularity (of sub-commands) can provide efficient management of the access requests that can reduce a gap latency in processing multiple access requests.

公开(公告)号：US20220374150A1

公开(公告)日：2022-11-24

申请号：US17748644

申请日：2022-05-19

Applicant: Micron Technology, Inc.

Inventor： Antonino Caprì ,  Emanuele Confalonieri ,  Simone Corbetta ,  Michela Spagnolo

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods related to an adjustable timer component are described. A memory device includes, a memory controller coupled to the memory device comprising an adjustable timer component. The adjustable timer component is configured to receive a timer generation request and, responsive to receiving the request, store in a cache an active timer entry corresponding to a particular first address, generate a timer corresponding to an active timer entry and the particular first address, and monitor the timer to determine when the timer expires. Responsive to the expiration of the timer, dequeue the timer entry and invalidate the timer entry stored in the cache. The memory device can also include command logic configured to, prior to issuing a second command, query the cache of the adjustable timer component to determine if the cache includes an active timer entry corresponding to the particular second address.

公开(公告)号：US20210166775A1

公开(公告)日：2021-06-03

申请号：US17170386

申请日：2021-02-08

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Marco Dallabora ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri

IPC: G11C29/42 ,  G11C29/44 ,  G11C13/00 ,  G11C7/22 ,  G06F11/10

Abstract: An example apparatus includes a memory comprising a plurality of managed units corresponding to respective groups of resistance variable memory cells and a controller coupled to the memory. The controller is configured to cause performance of a cleaning operation on a selected group of the memory cells and generation of error correction code (ECC) parity data. The controller may be further configured to cause performance of a write operation on the selected group of cells to write an inverted state of at least one data value to the selected group of cells and write an inverted state of at least one of the ECC parity data to the selected group of cells.

公开(公告)号：US20200301841A1

公开(公告)日：2020-09-24

申请号：US16893982

申请日：2020-06-05

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Dallabora ,  Roberto Izzi ,  Paolo Amato ,  Daniele Balluchi ,  Luca Porzio

IPC: G06F12/0862 ,  G06F12/10 ,  G06F3/06

Abstract: An example apparatus comprises a hybrid memory system and a controller coupled to the hybrid memory system. The controller may be configured to cause data to be selectively stored in the hybrid memory system responsive to a determination that an exception involving the data has occurred.

公开(公告)号：US20190206452A1

公开(公告)日：2019-07-04

申请号：US15857704

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Stefano Ratti ,  Gary G. Lazarowics ,  Stefan Frederik Schippers ,  Stefano Claudio Roseghini ,  Angelo Clemente Scardilla

IPC: G11C7/04 ,  G01K3/00 ,  G11C16/26 ,  G11C16/34 ,  G11C13/00 ,  G06F3/06

CPC classification number: G11C7/04 ,  G01K3/005 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0679 ,  G11C13/0033 ,  G11C16/26 ,  G11C16/3431

Abstract: Apparatuses, methods, and devices that can be utilized to provide temperature-based memory operations are described. One or more apparatuses can include a memory device and a controller coupled to the memory device and configured to: determine an operating temperature of the apparatus, determine one of a plurality of designated open blocks of the memory device to write data based on the operating temperature of the apparatus and a size of the data, and write the data in the determined one of the plurality of designated blocks of the memory device.

公开(公告)号：US10175908B2

公开(公告)日：2019-01-08

申请号：US15862472

申请日：2018-01-04

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Graziano Mirichigni ,  Gianfranco Santopietro ,  Gianfranco Ferrante ,  Emanuele Confalonieri

IPC: G06F3/06

Abstract: A controller of a memory device controls placement of data blocks by receiving, from a host electronic device, one or more commands of a memory system protocol. The commands include a write command with blocks of data to be stored in the memory device and contextual file system data for the blocks of data. The contextual file system data includes file metadata, file attributes, or both that identify an association of the one or more blocks of data with a file. The file is made up of the one or more blocks of data. The controller identifies the association of the one or more blocks of data with the file and executes the one or more commands, such that the one or more blocks of data are stored in the memory device with a placement based upon the association.

公开(公告)号：US20180129424A1

公开(公告)日：2018-05-10

申请号：US15345919

申请日：2016-11-08

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Marco Dallabora ,  Paolo Amato ,  Danilo Caraccio ,  Daniele Balluchi

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/10 ,  G11C13/00

CPC classification number: G06F3/0611 ,  G06F3/061 ,  G06F3/0647 ,  G06F3/0649 ,  G06F3/0658 ,  G06F3/068 ,  G06F3/0685 ,  G11C11/005 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26

Abstract: The present disclosure includes apparatuses, methods, and systems for data relocation in hybrid memory. A number of embodiments include a memory, wherein the memory includes a first type of memory and a second type of memory, and a controller configured to identify a subset of data stored in the first type of memory to relocate to the second type of memory based, at least in part, on a frequency at which an address corresponding to the subset of data stored in the first type of memory has been accessed during program operations performed on the memory.