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    FRONT END OF LINE INTERCONNECT STRUCTURES AND ASSOCIATED SYSTEMS AND METHODS
    21.
    发明申请
    FRONT END OF LINE INTERCONNECT STRUCTURES AND ASSOCIATED SYSTEMS AND METHODS 有权

    公开(公告)号：US20220068819A1

    公开(公告)日：2022-03-03

    申请号：US17325069

    申请日：2021-05-19

    Applicant: Micron Technology, Inc.

    Inventor： Kyle K. Kirby ,  Kunal R. Parekh

    IPC: H01L23/538 ,  H01L27/06 ,  H01L27/092 ,  H01L21/50 ,  H01L21/768

    Abstract: Systems and methods for a semiconductor device having a front-end-of-line interconnect structure are provided. The semiconductor device may include a dielectric material having a backside formed on a front side of a semiconductor or silicon substrate material and a front side, and a conducting material on the front side of the dielectric material. The conducting material may have a line portion and an interconnect structure electrically coupled to the line portion and separated from the front side of the substrate material by the dielectric material. The interconnect structure has a backside defining a contact surface. The semiconductor device may further include a semiconductor die proximate the front side of the dielectric material, an insulating material encasing at least a portion of the semiconductor die, and an opening through which the active contact surface at the backside of the interconnect structure is exposed for electrical connection.

    METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND ELECTRONIC SYSTEMS
    22.
    发明申请
    METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND ELECTRONIC SYSTEMS 有权

    公开(公告)号：US20210398859A1

    公开(公告)日：2021-12-23

    申请号：US16905763

    申请日：2020-06-18

    Applicant: Micron Technology, Inc.

    Inventor： Kunal R. Parekh

    IPC: H01L21/8234 ,  H01L21/768 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/528

    Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure; a doped semiconductive material overlying the base structure; a stack structure overlying the doped semiconductive material; semiconductive structures extending from within the base structure, through the doped semiconductive structure, and into a lower portion of the stack structure; cell pillar structures horizontally aligned with the semiconductive structures and vertically extending through an upper portion of the stack structure; and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form an assembly. The base structure and portions of the semiconductive structures are removed. The doped semiconductive material is then patterned to form at least one source structure coupled to the cell pillar structures. Devices and systems are also described.

    Integrated Assemblies and Methods of Forming Integrated Assemblies
    25.
    发明申请
    Integrated Assemblies and Methods of Forming Integrated Assemblies 审中-公开

    公开(公告)号：US20200058663A1

    公开(公告)日：2020-02-20

    申请号：US16663068

    申请日：2019-10-24

    Applicant: Micron Technology, Inc.

    Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

    IPC: H01L27/11524 ,  H01L27/11553 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11551

    Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

    Integrated structures
    26.
    发明授权
    Integrated structures 有权

    公开(公告)号：US10355018B1

    公开(公告)日：2019-07-16

    申请号：US16290169

    申请日：2019-03-01

    Applicant: Micron Technology, Inc.

    Inventor： Justin B. Dorhout ,  David Daycock ,  Kunal R. Parekh ,  Martin C. Roberts ,  Yushi Hu

    IPC: H01L27/088 ,  H01L21/336 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/78 ,  H01L29/76

    Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.

    Semiconductor devices, memory devices, and related methods
    28.
    发明授权
    Semiconductor devices, memory devices, and related methods 有权

    公开(公告)号：US10158071B2

    公开(公告)日：2018-12-18

    申请号：US15669484

    申请日：2017-08-04

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Kunal R. Parekh

    IPC: H01L23/48 ,  H01L45/00 ,  H01L21/033 ,  H01L21/768 ,  H01L27/24 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

    Abstract: Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.

    Arrays of memory cells and methods of forming an array of memory cells
    29.
    发明授权
    Arrays of memory cells and methods of forming an array of memory cells 有权

    公开(公告)号：US10068947B2

    公开(公告)日：2018-09-04

    申请号：US15375507

    申请日：2016-12-12

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Kunal R. Parekh

    IPC: H01L27/24 ,  H01L45/00

    Abstract: An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines. The pillars individually include a memory cell. Outer access lines are elevationally outward of the pillars and the buried access lines. The outer access lines are of higher electrical conductivity than the buried access lines. A plurality of conductive vias is spaced along and electrically couple pairs of individual of the buried and outer access lines. A plurality of the pillars is between immediately adjacent of the vias along the pairs. Electrically conductive metal material is directly against tops of the buried access lines and extends between the pillars along the individual buried access lines. Other embodiments, including method, are disclosed.

    Arrays of memory cells and methods of forming an array of memory cells
    30.
    发明授权
    Arrays of memory cells and methods of forming an array of memory cells 有权

    公开(公告)号：US10014347B2

    公开(公告)日：2018-07-03

    申请号：US15852275

    申请日：2017-12-22

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Kunal R. Parekh

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2463 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

    Abstract: An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines. The pillars individually include a memory cell. Outer access lines are elevationally outward of the pillars and the buried access lines. The outer access lines are of higher electrical conductivity than the buried access lines. A plurality of conductive vias is spaced along and electrically couple pairs of individual of the buried and outer access lines. A plurality of the pillars is between immediately adjacent of the vias along the pairs. Electrically conductive metal material is directly against tops of the buried access lines and extends between the pillars along the individual buried access lines. Other embodiments, including method, are disclosed.

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