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公开(公告)号：US20180365293A1
公开(公告)日：2018-12-20
申请号：US16113055
申请日：2018-08-27
发明人： Luca De Santis , Giulio G. Marotta , Marco-Domenico Tiburzi , Tommaso Vali , Frankie F. Roohparvar , Agostino Macerola
IPC分类号： G06F17/30 , G11C16/04 , G11C29/50 , G06F12/0802 , G06F3/06 , G06F7/20 , G11C7/10 , G11C16/06 , G11C15/04
CPC分类号： G06F16/24558 , G06F3/0628 , G06F7/20 , G06F12/0802 , G06F2212/1021 , G06F2212/608 , G11C7/1006 , G11C15/046 , G11C16/0483 , G11C16/06 , G11C29/50004 , G11C29/50016
摘要： Memory devices for facilitating pattern matching and having an array of memory cells, a plurality of key registers to store a representation of a key word, and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells.
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公开(公告)号：US10157644B1
公开(公告)日：2018-12-18
申请号：US15671317
申请日：2017-08-08
摘要： Methods of operating a voltage generation circuit, and apparatus configured to perform such methods, include applying a clock signal to an input of a voltage driver of a stage of the voltage generation circuit, connecting the voltage driver output to a first voltage node configured to receive a first voltage when the clock signal has a particular logic level and a voltage level of the voltage driver output is less than a threshold, connecting the voltage driver output to a second voltage node configured to receive a second voltage greater than the first voltage when the clock signal has the particular logic level and the voltage level of the voltage driver output is greater than the threshold, and connecting the voltage driver output to a third voltage node configured to receive a third voltage less than the first voltage when the clock signal has a different logic level.
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公开(公告)号：US09236102B2
公开(公告)日：2016-01-12
申请号：US13651093
申请日：2012-10-12
摘要： Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition.
摘要翻译： 公开了用于偏置存储器阵列中的信号线的装置，电路和方法。 在一个这样的示例中，存储器阵列包括耦合到多个存储器单元的信号线，并且被配置为响应于信号线的偏置条件来提供对多个存储器单元的访问。 存储器阵列还包括耦合到信号线的信号线驱动器，信号线驱动器被配置为向信号线提供偏置信号，并且响应于控制信号在偏置信号中提供预加重。 控制信号响应于操作状态。
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公开(公告)号：US11189536B2
公开(公告)日：2021-11-30
申请号：US16294469
申请日：2019-03-06
发明人： Kenneth William Marr , Chiara Cerafogli , Michele Piccardi , Marco-Domenico Tiburzi , Eric Higgins Freeman , Joshua Daniel Tomayer
摘要： A microelectronic chip device includes a semiconductor substrate and multiple on-chip strain sensors (OCSSs) constructed on the substrate at various locations of the substrate. The OCSSs may each include multiple piezoresistive devices configured to sense a strain at a location of the various locations and produce a strain signal representing the strain at that location. A strain measurement circuit may also be constructed on the semiconductor substrate and configured to measure strain parameters from the strain signals produced by the OCSSs. The strain parameters represent the strains at the various location. Values of the strain parameters can be used for analysis of mechanical stress on the chip device.
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公开(公告)号：US10923200B2
公开(公告)日：2021-02-16
申请号：US16745514
申请日：2020-01-17
摘要： Methods of operating a memory, as well as memory configured to perform such method, include applying an intermediate read voltage to a selected access line for a read operation, adding noise to a sensing operation while applying the intermediate read voltage, determining a value indicative of a number of memory cells of a plurality of memory cells connected to the selected access line that are activated in response to applying the intermediate read voltage to the selected access line, and determining a plurality of read voltages for the read operation in response to the value indicative of the number of memory cells of the plurality of memory cells that are activated in response to applying the intermediate read voltage to the selected access line.
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公开(公告)号：US10776362B2
公开(公告)日：2020-09-15
申请号：US16113055
申请日：2018-08-27
发明人： Luca De Santis , Giulio G. Marotta , Marco-Domenico Tiburzi , Tommaso Vali , Frankie F. Roohparvar , Agostino Macerola
IPC分类号： G06F3/06 , G06F16/2455 , G11C16/06 , G11C7/10 , G11C15/04 , G11C16/04 , G06F7/20 , G06F12/0802 , G11C29/50
摘要： Memory devices for facilitating pattern matching and having an array of memory cells, a plurality of key registers to store a representation of a key word, and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells.
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公开(公告)号：US20200160892A1
公开(公告)日：2020-05-21
申请号：US16774182
申请日：2020-01-28
IPC分类号： G11C5/14 , G06F1/3203 , G06F1/3234 , G05F3/16 , G11C16/30
摘要： Charge pumps of integrated circuit devices might include an input configured to receive an internally-generated first voltage level, an output, and a plurality of stages between its input and output. A particular stage might include a voltage isolation device, a voltage driver, and a capacitance having a first electrode connected to an output of the voltage driver and a second electrode connected to the voltage isolation device. The voltage driver might be responsive to a clock signal and to a voltage level of the output of the voltage driver to selectively connect the output of the voltage driver to either a first voltage node configured to receive the first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, or a third voltage node configured to receive a third voltage level lower than the second voltage level
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公开(公告)号：US10210928B2
公开(公告)日：2019-02-19
申请号：US14510950
申请日：2014-10-09
摘要： Apparatus, devices, systems, and methods are described that include variable state material data storage. Example devices include current compliance circuits that are configured to dynamically adjust a current passing through a variable resistance material during a memory operation. Some configurations utilize components within an array of memory cells to form a current compliance circuit. Additional apparatus, systems, and methods are described.
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公开(公告)号：US20190051334A1
公开(公告)日：2019-02-14
申请号：US16118724
申请日：2018-08-31
摘要： Voltage generation circuits include a stage including a voltage driver having inputs connected to respective voltage nodes and a clock signal, and a stage capacitance having a first electrode connected to an output of the voltage driver and a second electrode connected to a voltage isolation device. The voltage driver might be configured to connect its output to receive a first voltage when the clock signal has a particular logic level and a voltage level of its output is less than a threshold, to connect its output to receive a second voltage greater than the first voltage when the clock signal has the particular logic level and the voltage level of its output is greater than the threshold, and to connect its output to receive a third voltage less than the first voltage when the clock signal has a different logic level.
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公开(公告)号：US20180174625A1
公开(公告)日：2018-06-21
申请号：US15895290
申请日：2018-02-13
摘要： Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition.
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