公开(公告)号：US20210091009A1

公开(公告)日：2021-03-25

申请号：US16579577

申请日：2019-09-23

Applicant: Micron Technology, Inc.

Inventor： Devesh Kumar Datta ,  David Daycock ,  Keen Wah Chow ,  Tom George ,  Justin B. Dorhout ,  Bingli Ma ,  Rita J. Klein ,  John Mark Meldrim

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

Abstract: Some embodiments include a memory device having a conductive structure which includes silicon-containing material. A stack is over the conductive structure and includes alternating insulative levels and conductive levels. Channel material pillars extend through the stack and are electrically coupled with the conductive structure. Memory cells are along the channel material pillars. A conductive barrier material is under the silicon-containing material. The conductive barrier material includes one or more metals in combination with one or more nonmetals. An electrical contact is under the conductive barrier material. The electrical contact includes a region reactive with silicon. Silicon is precluded from reaching said region at least in part due to the conductive barrier material. Control circuitry is under the electrical contact and is electrically coupled with the conductive structure through at least the electrical contact and the conductive barrier material.

公开(公告)号：US10943920B2

公开(公告)日：2021-03-09

申请号：US16738499

申请日：2020-01-09

Applicant: Micron Technology, Inc.

Inventor： John M. Meldrim ,  Yushi Hu ,  Rita J. Klein ,  John D. Hopkins ,  Hongbin Zhu ,  Gordon A. Haller ,  Luan C. Tran

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/28 ,  H01L29/49

Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.

公开(公告)号：US20200343262A1

公开(公告)日：2020-10-29

申请号：US16927084

申请日：2020-07-13

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Rita J. Klein

IPC: H01L27/11582 ,  G06F3/06 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

Abstract: A memory array comprises a vertical stack comprising alternating insulative tiers and wordline tiers. The wordline tiers comprise gate regions of individual memory cells. The gate regions individually comprise part of a wordline in individual of the wordline tiers. Channel material extends elevationally through the insulative tiers and the wordline tiers. The individual memory cells comprise a memory structure laterally between the gate region and the channel material. Individual of the wordlines comprise laterally-outer longitudinal-edge portions and a respective laterally-inner portion laterally adjacent individual of the laterally-outer longitudinal-edge portions. The individual laterally-outer longitudinal-edge portions project upwardly and downwardly relative to its laterally-adjacent laterally-inner portion. Methods are disclosed.

公开(公告)号：US20200152658A1

公开(公告)日：2020-05-14

申请号：US16738499

申请日：2020-01-09

Applicant: Micron Technology, Inc.

Inventor： John M. Meldrim ,  Yushi Hu ,  Rita J. Klein ,  John D. Hopkins ,  Hongbin Zhu ,  Gordon A. Haller ,  Luan C. Tran

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/28 ,  H01L29/49

Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.

公开(公告)号：US10607851B2

公开(公告)日：2020-03-31

申请号：US15686526

申请日：2017-08-25

Applicant: Micron Technology, Inc.

Inventor： Andrew L. Li ,  Prashant Raghu ,  Sanjeev Sapra ,  Rita J. Klein ,  Sanh D. Tang ,  Sourabh Dhir

IPC: H01L21/00 ,  H01L21/311 ,  H01L21/02 ,  H01L27/108 ,  H01L21/66 ,  H01L21/67 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: Various embodiments comprise methods of selectively etching oxides over nitrides in a vapor-etch cyclic process. In one embodiment, the method includes, in a first portion of the vapor-etch cyclic process, exposing a substrate having oxide features and nitride features formed thereon to selected etchants in a vapor-phase chamber; transferring the substrate to a post-etch heat treatment chamber; and heating the substrate to remove etchant reaction products from the substrate. In a second portion of the vapor-etch cyclic process, the method continues with transferring the substrate from the post-etch heat treatment chamber to the vapor-phase chamber; exposing the substrate to the selected etchants in the vapor-phase chamber; transferring the substrate to the post-etch heat treatment chamber; and heating the substrate to remove additional etchant reaction products from the substrate. Apparatuses for performing the method and additional methods are also disclosed.

公开(公告)号：US10553611B2

公开(公告)日：2020-02-04

申请号：US16413498

申请日：2019-05-15

Applicant: Micron Technology, Inc.

Inventor： John M. Meldrim ,  Yushi Hu ,  Rita J. Klein ,  John D. Hopkins ,  Hongbin Zhu ,  Gordon A. Haller ,  Luan C. Tran

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L21/28 ,  H01L29/49

Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.

公开(公告)号：US10163655B2

公开(公告)日：2018-12-25

申请号：US14948074

申请日：2015-11-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jin Lu ,  Rita J. Klein ,  Diem Thy N. Tran ,  Irina V. Vasilyeva ,  Zhiqiang Xie

IPC: H01L29/40 ,  H01L21/321 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/48

Abstract: Apparatuses and methods are disclosed herein for densification of through substrate insulating liners. An example method may include forming a through substrate via through at least a portion of a substrate, forming a first liner layer in the through substrate via, and densifying the first liner layer. The example method may further include forming a second liner layer on the first liner layer, and densifying the second liner layer.

公开(公告)号：US12295140B2

公开(公告)日：2025-05-06

申请号：US17533580

申请日：2021-11-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Allen McTeer ,  Rita J. Klein ,  John D. Hopkins ,  Nancy M. Lomeli ,  Xiao Li ,  Alyssa N. Scarbrough ,  Jiewei Chen ,  Naiming Liu ,  Shuangqiang Luo ,  Silvia Borsari ,  John Mark Meldrim ,  Shen Hu

IPC: H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. A through-array-via (TAV) region comprises TAV constructions that extend through the insulative tiers and the conductive tiers. The TAV constructions individually comprise a radially-outer insulative lining and a conductive core radially-inward of the insulative lining. The insulative lining comprises a radially-inner insulative material and a radially-outer insulative material that are of different compositions relative one another. The radially-outer insulative material is in radially-outer recesses that are in the first tiers as compared to the second tiers. The radially-inner insulative material extends elevationally along the insulative tiers and the conductive tiers. Other embodiments, including method, are disclosed.

公开(公告)号：US12034057B2

公开(公告)日：2024-07-09

申请号：US17496715

申请日：2021-10-07

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Rita J. Klein ,  Everett A. McTeer ,  John Mark Meldrim

IPC: H10B43/27 ,  H01L29/49 ,  H10B41/27 ,  H10B41/10 ,  H10B43/10

CPC classification number: H01L29/4966 ,  H10B41/27 ,  H10B43/27 ,  H10B41/10 ,  H10B43/10

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. The wordline levels include conductive regions which have a first metal-containing material and a second metal-containing material. The first metal-containing material at least partially surrounds the second metal-containing material. The first metal-containing material has a different crystallinity than the second metal-containing material. In some embodiments the first metal-containing material is substantially amorphous, and the second metal-containing material has a mean grain size within a range of from greater than or equal to about 5 nm to less than or equal to about 200 nm. Charge-storage regions are adjacent the wordline levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.

公开(公告)号：US20220238444A1

公开(公告)日：2022-07-28

申请号：US17658907

申请日：2022-04-12

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Rita J. Klein ,  Everett A. McTeer ,  Lifang Xu ,  Daniel Billingsley ,  Collin Howder

IPC: H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

Abstract: A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.