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公开(公告)号：US20140351663A1
公开(公告)日：2014-11-27
申请号：US14263736
申请日：2014-04-28
Applicant: Micron Technology, Inc.
Inventor： Vishal Sarin , Aaron Yip , Tomoharu Tanaka
IPC: G11C29/50
CPC classification number: G11C29/50004 , G11C11/5628 , G11C16/0483 , G11C16/3459 , G11C2029/5004 , G11C2211/5621
Abstract: Memory devices and methods of operating memory devices are shown. Configurations described include circuits to perform a single check between programming pulses to determine a threshold voltage with respect to desired benchmark voltages. In one example, the benchmark voltages are used to change a programming speed of selected memory cells.
Abstract translation: 显示了存储器件和操作存储器件的方法。 所描述的配置包括在编程脉冲之间执行单次检查以确定相对于期望的基准电压的阈值电压的电路。 在一个示例中，基准电压用于改变所选存储单元的编程速度。
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22.发明申请公开(公告)号：US20140204693A1
公开(公告)日：2014-07-24
申请号：US14224543
申请日：2014-03-25
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Vishal Sarin , Dzung H. Nguyen , William H. Radke
IPC: G11C29/04
CPC classification number: G11C29/04 , G11C29/808 , G11C29/82 , G11C29/848
Abstract: In an embodiment, a defective memory block is replaced with a non-defective memory block, and a voltage-delay correction is applied to the non-defective memory block that replaces the defective memory block based on the actual location of the non-defective memory block.
Abstract translation: 在一个实施例中，有缺陷的存储器块被替换为非缺陷存储块，并且电压延迟校正被应用于基于无缺陷存储器的实际位置替换缺陷存储块的无缺陷存储器块 块。
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23.发明授权Programming error correction code into a solid state memory device with varying bits per cell 有权将错误纠正码编程成固态存储器件，每个单元具有不同位数公开(公告)号：US08719665B2
公开(公告)日：2014-05-06
申请号：US14056031
申请日：2013-10-17
Applicant: Micron Technology, Inc.
Inventor： Frankie F. Roohparvar , Vishal Sarin , Jung S. Hoei
CPC classification number: G06F11/1076 , G06F11/1072 , G11C29/12005
Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.
Abstract translation: 在特定实施例中，存储设备接收和发送表示两个或多个位的位模式的模拟数据信号，以便于相对于传送指示各个位的数据信号的设备的数据传输速率的增加。 编程错误校正码（ECC）和元数据到这种存储器设备中包括基于单元的实际错误率将ECC和元数据存储在每个小区的不同比特级。 ECC和元数据可以与数据块存储在与数据块不同的位级别。 如果其中存储数据块的存储器区域不支持在特定位级别的ECC和元数据的期望的可靠性，则ECC和元数据可以以不同的位电平存储在存储器阵列的其他区域中。
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公开(公告)号：US20140104956A1
公开(公告)日：2014-04-17
申请号：US14104444
申请日：2013-12-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jonathan Pabustan , Vishal Sarin , Dzung H. Nguyen
IPC: G11C16/10
CPC classification number: G06F3/0613 , G06F3/0655 , G06F3/0679 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/32 , G11C16/3454 , G11C16/3459
Abstract: Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells being sensed. Target data for each memory cell is stored in a data cache associated with that particular memory cell. When it is detected that a memory cell has turned on, the translated count output associated with the count output that is indicative of the voltage level that turned on the memory cell is compared to the target data. The comparison determines the state of the memory cell.
Abstract translation: 公开了感测方法，编程方法，存储器件和存储器系统。 在一种用于感测的方法中，计数电路产生计数输出和转换计数输出。 计数输出被转换成时变电压，该电压偏置耦合到被感测的存储器单元的字线。 每个存储器单元的目标数据被存储在与该特定存储器单元相关联的数据高速缓存器中。 当检测到存储器单元已经接通时，将与指示存储器单元接通的电压电平的计数输出相关联的转换计数输出与目标数据进行比较。 比较确定存储单元的状态。
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公开(公告)号：US08693246B2
公开(公告)日：2014-04-08
申请号：US13749850
申请日：2013-01-25
Applicant: Micron Technology, Inc.
Inventor： Frankie F. Roohparvar , Vishal Sarin , Jung-Sheng Hoei
CPC classification number: G11C16/10 , G11C16/04 , G11C16/20 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C29/50004 , G11C2029/5004
Abstract: Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming operations, the voltage on the selected cell is read to determine any change in voltage caused by systemic offsets such as, for example, floating gate-to-floating gate coupling. These changes are averaged and stored in a table as an offset for use in adjusting a programming voltage or a read voltage in a particular area of memory represented by the offset. Self calibration method for temperature is determined by writing cells at different temperatures and reading at different temperatures to generate temperature offset tables for the write path and read path. These offset tables are used to adjust for systematic temperature related offsets during programming and during read.
Abstract translation: 通过向所选择的单元写入电压来执行存储器控制器的自校准。 对所选单元格周围的相邻单元进行编程。 在每个相邻的编程操作之后，读取所选择的单元上的电压，以确定由例如浮动栅极到浮置栅极耦合的系统偏移引起的任何电压变化。 这些变化被平均并存储在表中作为用于调整由偏移表示的存储器的特定区域中的编程电压或读取电压的偏移。 通过在不同温度下写入单元格并在不同温度读取来确定温度的自校准方法，以生成写入路径和读取路径的温度偏移表。 这些偏移表用于在编程期间和读取期间调整与系统温度相关的偏移。
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Patent Agency Ranking
公开(公告)号：US11222699B2
公开(公告)日：2022-01-11
申请号：US17010334
申请日：2020-09-02
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Vishal Sarin , Allahyar Vahidimowlavi
Abstract: Memory having an array of memory cells might include control logic configured to cause the memory to inhibit memory cells of a first subset of memory cells from programming during each programming pulse of a first plurality of programming pulses and enable those memory cells for programming for at least one programming pulse of a second plurality of programming pulses, inhibit memory cells of a second subset of memory cells from programming during each programming pulse of the second plurality of programming pulses and enable those memory cells for programming for at least one programming pulse of the first plurality of programming pulses, and enable memory cells of a third subset of memory cells for programming during at least one programming pulse of the first plurality of programming pulses and during at least one programming pulse of the second plurality of programming pulses.
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公开(公告)号：US11205481B2
公开(公告)日：2021-12-21
申请号：US17218243
申请日：2021-03-31
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Luca De Santis , Tommaso Vali , Kenneth J. Eldredge , Vishal Sarin
Abstract: Memory devices might include control circuitry that, when checking for a match of a stored digit of data and a received digit of data, might be configured to cause the memory device to apply a first voltage level to a control gate of a first memory cell of a memory cell pair, apply a second voltage level different than the first voltage level to a control gate of a second memory cell of that memory cell pair, determine whether that memory cell pair is deemed to be activated or deactivated in response to applying the first and second voltage levels, and deem a match between the stored digit of data and a received digit of data in response, in part, to whether that memory cell pair is deemed to be deactivated.
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公开(公告)号：US10141055B2
公开(公告)日：2018-11-27
申请号：US15841490
申请日：2017-12-14
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Luca De Santis , Tommaso Vali , Kenneth J. Eldredge , Vishal Sarin
Abstract: Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.
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公开(公告)号：US20170025170A1
公开(公告)日：2017-01-26
申请号：US15287956
申请日：2016-10-07
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Vishal Sarin , Allahyar Vahidimowlavi
CPC classification number: G11C11/5628 , G11C16/0408 , G11C16/0458 , G11C16/10 , G11C16/3418 , G11C16/3427 , G11C2211/562 , G11C2211/5622 , G11C2211/5642 , G11C2211/5648
Abstract: A first memory cell is programmed to a first level using a first set of program pulses within a first programming voltage range. A second memory cell to be programmed to a second level less than the first level is inhibited while programing the first memory cell to the first level. After programing the first memory cell to the first level, the second memory cell is programmed to the second level using a second set of program pulses within a second programming voltage range, where the first programming voltage range overlaps the second programming voltage range. The first memory cell that is programmed to the first level is inhibited while programing the second memory cell to the second level.
Abstract translation: 使用第一编程电压范围内的第一组编程脉冲将第一存储单元编程为第一电平。 在将第一存储器单元编程到第一级时，禁止要编程到小于第一级的第二级的第二存储器单元。 在将第一存储器单元编程到第一电平之后，使用第二编程电压范围内的第二组编程脉冲将第二存储单元编程到第二电平，其中第一编程电压范围与第二编程电压范围重叠。 在将第二存储器单元编程到第二级时，禁止编程到第一级的第一存储器单元。
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公开(公告)号：US09423969B2
公开(公告)日：2016-08-23
申请号：US14827371
申请日：2015-08-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jonathan Pabustan , Vishal Sarin , Dzung H. Nguyen
CPC classification number: G06F3/0613 , G06F3/0655 , G06F3/0679 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/32 , G11C16/3454 , G11C16/3459
Abstract: Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells being sensed. Target data for each memory cell is stored in a data cache associated with that particular memory cell. When it is detected that a memory cell has turned on, the translated count output associated with the count output that is indicative of the voltage level that turned on the memory cell is compared to the target data. The comparison determines the state of the memory cell.
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