公开(公告)号：US10770144B1

公开(公告)日：2020-09-08

申请号：US16277877

申请日：2019-02-15

Applicant: MACRONIX International Co., Ltd.

Inventor： Hsing-Wen Chang ,  Yao-Wen Chang

IPC: G11C16/10 ,  G11C16/24 ,  G11C16/08 ,  H01L27/115

Abstract: A non-volatile memory and a program method thereof are provided. The program method includes: setting one of a plurality of word lines to be a program word line, setting the word lines except the program word line to be a plurality of unselected word lines; raise a voltage on the program word line from a reference voltage to a first program voltage during a first sub-time period of a program time period; raising the voltage on the program word line from the first program voltage to a second program voltage during a second sub-time period of the program time period; and raising voltages on at least part of the unselected word lines from the reference voltage to a pass voltage during the second sub-time period.

公开(公告)号：US10741262B2

公开(公告)日：2020-08-11

申请号：US16212551

申请日：2018-12-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Liang Lin ,  Chun-Chang Lu ,  Wen-Jer Tsai ,  Guan-Wei Wu ,  Yao-Wen Chang

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C8/08 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11524

Abstract: A programming operation for high density memory, like 3D NAND flash memory, modifies the waveforms applied during program operations to mitigate unwanted disturbance of memory cells not selected for programming during the operation. Generally, the method provides for applying a bias arrangement during an interval of time between program verify pass voltages and program pass voltages in a program sequence that can include a soft ramp down, and pre-turn-on voltages designed to reduce variations in the potential distribution on floating channels of unselected NAND strings during a program operation.

公开(公告)号：US20170010321A1

公开(公告)日：2017-01-12

申请号：US14792148

申请日：2015-07-06

Applicant: MACRONIX International Co., Ltd.

Inventor： Shih-Yu Wang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC: G01R31/28

CPC classification number: G01R31/2853 ,  G01R1/0491 ,  G01R31/3004

Abstract: Latch-up test device and method are provided, and the method includes following steps. A set operation is performed for setting a basic test value according to a test range and setting a trigger pulse and a predetermined error value by the basic test value. A test on a test chip in a wafer under test is performed by the trigger pulse, and whether the test chip is in a latch-up state is determined. Whether to update a test range and a latch-up threshold value and whether to return to the step of performing the set operation are determined according to a determination result, the latch-up threshold value and the basic test value. When the test chip is in the latch-up state and a difference between the latch-up threshold value and the basic test value is not greater than the predetermined error value, the test on the test chip is stopped.

Abstract translation: 提供了锁存测试装置和方法，该方法包括以下步骤。 执行设定操作，根据测试范围设置基本测试值，并通过基本测试值设置触发脉冲和预定误差值。 通过触发脉冲进行被测晶片中的测试芯片的测试，并确定测试芯片是否处于闭锁状态。 根据确定结果，闩锁阈值和基本测试值来确定是否更新测试范围和锁存阈值以及是否返回到执行设置操作的步骤。 当测试芯片处于闩锁状态并且闩锁阈值和基本测试值之间的差异不大于预定误差值时，测试芯片上的测试被停止。

公开(公告)号：US09437303B1

公开(公告)日：2016-09-06

申请号：US14834809

申请日：2015-08-25

Applicant: MACRONIX International Co., Ltd.

Inventor： Chu-Yung Liu ,  Hsing-Wen Chang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3459

Abstract: A programming method of a memory array is provided and includes following steps, wherein the memory array includes a target memory cell and two periphery memory cells electrically connected to a first word line. After a first programming operation is performed on the target memory cell, the target memory cell and the two periphery memory cells are verified to obtain a first verification result. Whether to perform a second programming operation or a third programming operation on the target memory cell is determined according to the first verification result. The step of performing the second programming operation or the third programming operation on the target memory cell includes: turning off a first transistor and a second transistor; and increasing a level of a passing voltage for turning on a plurality of non-target memory cells and a level of a programming voltage transmitted by the first word line.

Abstract translation: 提供了存储器阵列的编程方法，并且包括以下步骤，其中存储器阵列包括电连接到第一字线的目标存储器单元和两个外围存储器单元。 在对目标存储单元执行第一编程操作之后，验证目标存储单元和两个周边存储单元以获得第一验证结果。 根据第一验证结果确定是否对目标存储单元执行第二编程操作或第三编程操作。 对目标存储单元执行第二编程操作或第三编程操作的步骤包括：关闭第一晶体管和第二晶体管; 以及增加用于接通多个非目标存储单元的通过电压的电平以及由第一字线发送的编程电压的电平。

公开(公告)号：US20160133718A1

公开(公告)日：2016-05-12

申请号：US14539768

申请日：2014-11-12

Applicant: MACRONIX International Co., Ltd.

Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  I-Chen Yang ,  Tao-Cheng Lu

IPC: H01L29/66

CPC classification number: H01L29/6656 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/26593 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66575 ,  H01L29/78

Abstract: Provided is a semiconductor device. Two stack layers are disposed on a substrate of a first conductivity type. Each of stack layers includes a dielectric layer and a conductive layer. The dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. First doped region of a second conductivity type has a first dopant and is disposed in the substrate between the stack layers. A pre-amorphization implantation (PAI) region is disposed in the first doped region. A second doped region of the second conductivity type has a second dopant and is disposed in the PAI region. The first conductivity type is different from the second conductivity type. A diffusion rate of the second dopant is faster than a diffusion rate of the first dopant, and a thermal activation of the second dopant is higher than that of the first dopant.

Abstract translation: 提供一种半导体器件。 两个堆叠层设置在第一导电类型的衬底上。 每个堆叠层包括电介质层和导电层。 电介质层设置在基板上。 导电层设置在电介质层上。 第二导电类型的第一掺杂区具有第一掺杂剂并且被布置在堆叠层之间的衬底中。 在第一掺杂区域中设置预非晶化注入（PAI）区域。 第二导电类型的第二掺杂区域具有第二掺杂剂并且被布置在PAI区域中。 第一导电类型与第二导电类型不同。 第二掺杂剂的扩散速度比第一掺杂剂的扩散速度快，并且第二掺杂剂的热激活高于第一掺杂剂的扩散速率。

公开(公告)号：US20150200306A1

公开(公告)日：2015-07-16

申请号：US14154991

申请日：2014-01-14

Applicant: Macronix International Co., Ltd.

Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  I-Chen Yang ,  Tao-Cheng Lu

IPC: H01L29/792 ,  H01L21/266 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66833

Abstract: A non-volatile memory includes a substrate, a charge trapping structure disposed on the substrate, a buffer layer disposed on the charge trapping structure, and a plurality of conductive layers disposed on the buffer layer.

Abstract translation: 非易失性存储器包括衬底，设置在衬底上的电荷俘获结构，设置在电荷俘获结构上的缓冲层和设置在缓冲层上的多个导电层。

公开(公告)号：US08748963B1

公开(公告)日：2014-06-10

申请号：US13707426

申请日：2012-12-06

Applicant: MACRONIX International Co., Ltd.

Inventor： Guan-Wei Wu ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC: H01L21/4763

CPC classification number: H01L29/792 ,  H01L29/42352 ,  H01L29/66833

Abstract: A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory including a gate structure disposed on a substrate, doped regions, charge storage layers, and a first dielectric layer. There are recesses in the substrate at two sides of the gate structure. The gate structure includes a gate dielectric layer disposed on the substrate and a gate disposed on the gate dielectric layer. There is an interface between the gate dielectric layer and the substrate. The doped regions are disposed in the substrate around the recesses. The charge storage layers are disposed in the recesses, and a top surface of each of the charge storage layers is higher than the interface. The first dielectric layer is disposed between the charge storage layers and the substrate, and between the charge storage layers and the gate structure.

Abstract translation: 提供了一种非易失性存储器及其制造方法。 非易失性存储器包括设置在衬底上的栅极结构，掺杂区域，电荷存储层和第一介电层。 栅极结构两侧的基板上有凹槽。 栅极结构包括设置在衬底上的栅极电介质层和设置在栅极介电层上的栅极。 在栅介电层和衬底之间存在界面。 掺杂区域围绕凹部设置在基板中。 电荷存储层设置在凹部中，并且每个电荷存储层的顶表面高于界面。 第一介电层设置在电荷存储层与基板之间，电荷存储层与栅极结构之间。

公开(公告)号：US20140126296A1

公开(公告)日：2014-05-08

申请号：US14151617

申请日：2014-01-09

Applicant: MACRONIX International Co., Ltd.

Inventor： Hsing-Wen Chang ,  Yao-Wen Chang ,  Chu-Yung Liu

IPC: G11C16/08

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/3418

Abstract: A flash memory device including a memory array, a row decoder and M page buffers is provided, wherein M is an integer greater than 2. The memory array includes a plurality of memory cells and is connected to a plurality of word lines and a plurality of bit lines. The row decoder drives a specific word line among the word lines during an enabling period. Each of the page buffers is connected to N bit lines of the bit lines, and N is an integer equal to or greater than 3. A jth page buffer drives an (N*(j−1)+1)th bit line to an (N*j)th bit line during the enabling period, and one of an (i−1)th bit line and an (i+1)th bit line is not driven when an ith bit line is not driven, wherein j is an integer and 1≦j≦M, and i is an integer and 1

Abstract translation: 提供了包括存储器阵列，行解码器和M页缓冲器的闪速存储器件，其中M是大于2的整数。存储器阵列包括多个存储器单元，并且连接到多个字线和多个字线 位线。 行解码器在使能期间驱动字线中的特定字线。 每个页缓冲器连接到位线的N位线，N是等于或大于3的整数。第j页缓冲器驱动（N *（j-1）+1）位线到 （N * j）位线，并且当第i位线未被驱动时，不驱动第（i-1）位线和第（i + 1）位线之一，其中j为 整数和1＆nlE; j＆nlE; M，i是整数，1