公开(公告)号：US6048740A

公开(公告)日：2000-04-11

申请号：US187238

申请日：1998-11-05

申请人： Sheng Teng Hsu ,  Jer-shen Maa ,  Fengyang Zhang ,  Tingkai Li

发明人： Sheng Teng Hsu ,  Jer-shen Maa ,  Fengyang Zhang ,  Tingkai Li

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC分类号： H01L29/6684 ,  H01L29/78391

摘要： A method of fabricating a ferroelectric memory transistor using a lithographic process having an alignment tolerance of .delta., includes preparing a silicon substrate for construction of a ferroelectric gate unit; implanting boron ions to form a p- well in the substrate; isolating plural device areas on the substrate; forming a FE gate stack surround structure; etching the FE gate stack surround structure to form an opening having a width of L1 to expose the substrate in a gate region; depositing oxide to a thickness of between about 10 nm to 40 nm over the exposed substrate; forming a FE gate stack over the gate region, wherein the FE gate stack has a width of L2, wherein L2.gtoreq.L1+2.delta.; depositing a first insulating layer over the structure; implanting arsenic or phosphorous ions to form a source region and a drain region; annealing the structure; depositing a second insulating layer; and metallizing the structure. A ferroelectric memory transistor includes a silicon substrate having a p- well formed therein; a gate region, a source region and a drain region disposed along the upper surface of said substrate; a FE gate stack surround structure having an opening having a width of L1 located about said gate region; a FE gate stack formed in said FE gate stack surround structure, wherein said FE gate stack has a width of L2, wherein L2.gtoreq.L1+2.delta., wherein .delta. is the alignment tolerance of the lithographic process.

摘要翻译： 使用具有三角形对准公差的光刻工艺制造铁电存储晶体管的方法包括制备用于构造铁电栅极单元的硅衬底; 注入硼离子以在衬底中形成p-阱; 隔离基板上的多个器件区域; 形成一个FE门堆栈环绕结构; 蚀刻FE栅堆叠环绕结构以形成宽度为L1的开口，以在栅极区域中露出基板; 在暴露的衬底上沉积氧化物至约10nm至40nm的厚度; 在所述栅极区域上形成FE栅极堆叠，其中所述FE栅极堆叠具有L2的宽度，其中L2> / = L1 +2δ; 在所述结构上沉积第一绝缘层; 注入砷或磷离子以形成源区和漏区; 退火结构; 沉积第二绝缘层; 并且对结构进行金属化。 铁电存储晶体管包括其中形成有p-阱的硅衬底; 栅极区域，源极区域和漏极区域，沿着所述衬底的上表面设置; 具有开口的FE栅叠层环绕结构，所述开口具有围绕所述栅区的L1的宽度; 形成在所述FE栅极堆叠环绕结构中的FE栅极堆叠，其中所述FE栅极堆叠具有L2的宽度，其中L2> / = L1 +2δ，其中Δ是光刻工艺的对准公差。

公开(公告)号：US5814537A

公开(公告)日：1998-09-29

申请号：US768647

申请日：1996-12-18

申请人： Jer-shen Maa ,  Sheng Teng Hsu

发明人： Jer-shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/285

CPC分类号： H01L29/66772 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/665 ,  H01L2924/0002 ,  Y10S148/147

摘要： A method is provided for forming silicide surfaces on source, drain, and gate electrodes in active devices to decrease the resistance of the electrode surfaces, without consuming the silicon of the electrodes in the process. Silicide is directionally deposited on the electrodes so that a greater thickness accumulates on electrode surfaces, and a lesser thickness accumulates on the gate sidewall surfaces isolating the gate from the source/drain electrodes. Then, the electrodes are isotropically etched so that the lesser thickness on the sidewalls is removed, leaving at least some thickness of silicide covering the electrodes. In further steps, the electrodes are masked with photoresist, and any silicide deposited in the region of field oxide around the electrodes is removed. Conductive lines, connecting to the electrodes across the field oxide, are fabricated from polycide, which includes a level of polysilicon covered with silicide, when the lower resistance surface of a metal-disilicide overlying the conductive line is required. The method of the present invention is applicable to bulk silicon, as well as SIMOX, transistor fabrication processes. An IC structure having different thicknesses of directionally deposited silicide, and a completed MOS transistor having interim thicknesses of directionally deposited silicide, are also provided.

摘要翻译： 提供了一种用于在有源器件中的源极，漏极和栅电极上形成硅化物表面以降低电极表面的电阻而不消耗该工艺中的电极的硅的方法。 硅化物被定向沉积在电极上，使得更大的厚度积聚在电极表面上，并且较小的厚度积聚在栅极侧壁表面上，隔离栅极与源极/漏极电极。 然后，电极被各向同性地蚀刻，以便去除侧壁上较小的厚度，留下覆盖电极的至少一些厚度的硅化物。 在其他步骤中，电极被光致抗蚀剂掩蔽，并且去除沉积在电极周围的场氧化物区域中的任何硅化物。 当需要覆盖在导电线上的金属二硅化物的较低电阻表面时，由多晶硅半导体制造连接到场氧化物上的电极的导电线，其包括覆盖有硅化物的多晶硅层。 本发明的方法可应用于体硅，以及SIMOX晶体管制造工艺。 还提供了具有不同厚度的定向沉积的硅化物的IC结构和具有定向沉积的硅化物的中间厚度的完整的MOS晶体管。

公开(公告)号：US4585515A

公开(公告)日：1986-04-29

申请号：US710284

申请日：1985-03-11

申请人： Jer-shen Maa

发明人： Jer-shen Maa

IPC分类号： H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L21/306 ,  B44C1/22 ,  C03C15/00 ,  C23F1/02

CPC分类号： H01L21/31116 ,  H01L21/28 ,  H01L21/28052 ,  H01L21/7684 ,  H01L21/76889

摘要： A process of forming conductive lines of fine dimensions over a substrate having topographical features without the formation of conductive stringers is disclosed. Openings of the desired dimensions overlying the topographical features are lithographically defined in a layer of planarizing dielectric material deposited on the substrate. A layer of doped silicon is deposited thereover and isotropically etched to remove all except for the portion in the openings in the dielectric layer. A layer of metal is deposited to overlie only the silicon in the openings in the dielectric layer. The structure is annealed to convert the metal to metal silicide and the remaining dielectric layer is removed.

摘要翻译： 公开了一种在具有形貌特征的衬底上形成精细尺寸的导电线的过程，而不形成导电桁条。 覆盖地形特征的所需尺寸的开口在沉积在基底上的平坦化介电材料层中光刻地限定。 在其上沉积一层掺杂的硅，并进行各向同性蚀刻以去除除电介质层中的开口部分之外的所有物质。 沉积一层金属以仅覆盖电介质层的开口中的硅。 将该结构退火以将金属转化为金属硅化物，并除去剩余的介电层。

公开(公告)号：US20060073708A1

公开(公告)日：2006-04-06

申请号：US11284326

申请日：2005-11-21

申请人： Jer-shen Maa ,  Jong-Jan Lee ,  Douglas Tweet ,  David Evans ,  Allen Burmaster ,  Sheng Hsu

发明人： Jer-shen Maa ,  Jong-Jan Lee ,  Douglas Tweet ,  David Evans ,  Allen Burmaster ,  Sheng Hsu

IPC分类号： H01L21/324

CPC分类号： H01L21/76254

摘要： Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device channel and the limited silicon volume because of the insulator layer. The present invention discloses SSOI substrate fabrication processes comprising various novel approaches. One is the use of a thin relaxed SiGe layer as the strain-induced seed layer to facilitate integration and reduce processing cost. Another is the formation of split implant microcracks deep in the silicon substrate to reduce the number of threading dislocations reaching the strained silicon layer. And lastly is a two step annealing/thinning process for the strained silicon/SiGe multilayer film transfer without blister or flaking formation.

摘要翻译： 包含直接设置在绝缘体层上的应变硅层的SSOI（应变绝缘体硅）基板上制造的晶体管由于应变诱导的应变硅器件通道的带隙修改而增加了器件性能，并且由于 绝缘体层。 本发明公开了包含各种新颖方法的SSOI衬底制造工艺。 一个是使用薄的松弛SiGe层作为应变诱导的种子层，以促进整合并降低加工成本。 另一个是在硅衬底深部形成分裂的植入物微裂纹，以减少到达应变硅层的穿透位错的数量。 最后是对应变硅/ SiGe多层膜转移进行两步退火/变薄处理，无需起泡或剥落形成。

公开(公告)号：US06992025B2

公开(公告)日：2006-01-31

申请号：US10755615

申请日：2004-01-12

申请人： Jer-shen Maa ,  Jong-Jan Lee ,  Douglas J. Tweet ,  David R. Evans ,  Allen W. Burmaster ,  Sheng Teng Hsu

发明人： Jer-shen Maa ,  Jong-Jan Lee ,  Douglas J. Tweet ,  David R. Evans ,  Allen W. Burmaster ,  Sheng Teng Hsu

IPC分类号： H01L21/26 ,  H01L21/42 ,  H01L21/324

CPC分类号： H01L21/76254

摘要： Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device channel and the limited silicon volume because of the insulator layer. The present invention discloses a SSOI substrate fabrication process comprising various novel approaches. One is the use of a thin relaxed SiGe layer as the strain-induced seed layer to facilitate integration and reduce processing cost. Another is the formation of split implant microcracks deep in the silicon substrate to reduce the number of threading dislocations reaching the strained silicon layer. And lastly is the two step annealing/thinning process for the strained silicon/SiGe multilayer film transfer without blister or flaking formation.

摘要翻译： 包含直接设置在绝缘体层上的应变硅层的SSOI（应变绝缘体硅）基板上制造的晶体管由于应变诱导的应变硅器件通道的带隙修改而增加了器件性能，并且由于 绝缘体层。 本发明公开了一种包含各种新颖方法的SSOI衬底制造工艺。 一个是使用薄的松弛SiGe层作为应变诱导的种子层，以促进整合并降低加工成本。 另一个是在硅衬底深部形成分裂的植入物微裂纹，以减少到达应变硅层的穿透位错的数量。 最后是对应变硅/ SiGe多层膜转移的两步退火/变薄处理，没有起泡或剥落形成。

公开(公告)号：US20050151134A1

公开(公告)日：2005-07-14

申请号：US11073185

申请日：2005-03-03

申请人： Sheng Hsu ,  Jong-Jan Lee ,  Douglas Tweet ,  Jer-shen Maa

发明人： Sheng Hsu ,  Jong-Jan Lee ,  Douglas Tweet ,  Jer-shen Maa

IPC分类号： H01L21/322 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  H01L31/036

CPC分类号： H01L29/1054 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/78645

摘要： A dual gate strained-Si MOSFET with thin SiGe dislocation regions and a method for fabricating the same are provided. The method comprises: forming a first layer of relaxed SiGe overlying a substrate, having a thickness of less than 5000 Å; forming a second layer of relaxed SiGe overlying the substrate and adjacent to the first layer of SiGe, having a thickness of less than 5000 Å; forming a layer of strained-Si overlying the first and second SiGe layers; forming a shallow trench isolation region interposed between the first SiGe layer and the second SiGe layer; forming an n-well in the substrate and the overlying first layer of SiGe; forming a p-well in the substrate and the overlying second layer of SiGe; forming channel regions, in the strained-Si, and forming PMOS and NMOS transistor source and drain regions.

摘要翻译： 提供具有薄SiGe位错区域的双栅应变Si MOSFET及其制造方法。 该方法包括：形成覆盖衬底的第一层松弛SiGe，厚度小于5000; 形成第二层弛豫的SiGe，覆盖衬底并与第一层SiGe相邻，厚度小于5000; 形成层叠在第一和第二SiGe层上的应变层; 形成介于所述第一SiGe层和所述第二SiGe层之间的浅沟槽隔离区域; 在衬底和上覆的第一层SiGe中形成n阱; 在衬底和SiGe的上覆第二层中形成p阱; 在应变Si中形成沟道区，并形成PMOS和NMOS晶体管的源极和漏极区。

公开(公告)号：US06703293B2

公开(公告)日：2004-03-09

申请号：US10194383

申请日：2002-07-11

申请人： Douglas J. Tweet ,  Sheng Teng Hsu ,  Jer-shen Maa ,  Jong-Jan Lee

发明人： Douglas J. Tweet ,  Sheng Teng Hsu ,  Jer-shen Maa ,  Jong-Jan Lee

IPC分类号： H01L21265

CPC分类号： H01L21/02381 ,  C30B25/02 ,  C30B29/52 ,  C30B31/22 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02694 ,  Y10S438/933

摘要： A method of fabricating a Si1−XGeX film on a silicon substrate includes preparing a silicon substrate; epitaxially depositing a Si1−XGeX layer on the silicon substrate forming a Si1−XGeX/Si interface there between; amorphizing the Si1−XGeX layer at a temperature greater than Tc to form an amorphous, graded SiGe layer; and annealing the structure at a temperature of between about 650° C. to 1100° C. for between about ten seconds and sixty minutes to recrystallize the SiGe layer.

摘要翻译： 在硅衬底上制造Si1-XGeX膜的方法包括制备硅衬底; 在硅衬底上外延沉积形成Si1-XGeX / Si界面的Si1-XGeX层; 在大于Tc的温度下使Si1-XGeX层非晶化以形成无定形的梯度SiGe层; 并在约650℃至1100℃的温度下对该结构退火约十秒至六十分钟以使SiGe层重结晶。

公开(公告)号：US06585821B1

公开(公告)日：2003-07-01

申请号：US10345636

申请日：2003-01-15

申请人： Wei-Wei Zhuang ,  Fengyan Zhang ,  Jer-shen Maa ,  Sheng Teng Hsu

发明人： Wei-Wei Zhuang ,  Fengyan Zhang ,  Jer-shen Maa ,  Sheng Teng Hsu

IPC分类号： C23C1616

CPC分类号： H01L21/02197 ,  C01G21/00 ,  C01P2002/86 ,  H01L21/02112 ,  H01L21/02175 ,  H01L21/02282 ,  H01L21/31604 ,  H01L21/31691

摘要： A method of monitoring the synthesis of a PGO spin-coating precursor solution includes monitoring heating of the solution with a UV spectrometer and terminating the heating step when a solution property reaches a predetermined value. The method utilizes the starting materials of lead acetate trihydrate (Pb(OAc)2.3H2O) and germanium alkoxide (Ge(OR)4 (R=C2H5 and CH(CH3)2)). The organic solvent is di(ethylene glycol)ethyl ether. The mixed solution of lead and di(ethylene glycol)ethyl ether is heated in an atmosphere of air at a temperature no greater than 190° C., and preferably no greater than 185° C. for a time period in a range of approximately eighty-five minutes. During the heating step the solution properties are monitored to determine when the reaction is complete and when decomposition of the desired product begins to take place. The solution is then added to germanium di(ethylene glycol)ethyl ether to make the PGO spin-coating solution. This second step also entails heating the solution to a temperature no greater than 190° C. for a time period in a range of 0.5 to 2.0 hours. This heating step is also monitored with a UV spectrometer to determine when the heating step should be terminated. The process results in a PGO precursor solution suitable for use in spin-coating.

摘要翻译： 监测PGO旋涂前体溶液合成的方法包括用UV光谱仪监测溶液的加热，并且当溶液性能达到预定值时终止加热步骤。 该方法采用醋酸铅三水合物（Pb（OAc）2.3H2O）和烷氧基锗（Ge（OR）4（R = C2H5和CH（CH3）2））的原料。 有机溶剂是二（乙二醇）乙醚。 将铅和二（乙二醇）乙醚的混合溶液在不大于190℃，优选不大于185℃的空气气氛中加热约80℃的时间 -5分钟。 在加热步骤期间，监测溶液性质以确定反应何时完成，并且当所需产物的分解开始发生时。 然后将该溶液加入到二（乙二醇）二乙醚中以制备PGO旋涂溶液。 该第二步骤还需要将溶液加热至不高于190℃的温度，持续0.5至2.0小时的时间。 该加热步骤也用UV光谱仪监测，以确定加热步骤何时终止。 该方法产生适合用于旋涂的PGO前体溶液。

公开(公告)号：US06479304B1

公开(公告)日：2002-11-12

申请号：US09717993

申请日：2000-11-21

申请人： Fengyan Zhang ,  Jer-shen Maa ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Jer-shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L2100

CPC分类号： H01L28/75 ,  H01L21/28291 ,  H01L28/55 ,  H01L29/516

摘要： An Ir combination film has been provided that is useful in forming an electrode of a ferroelectric capacitor. The combination film includes tantalum and oxygen, as well as iridium. The Ir combination film effectively prevents oxygen diffusion, and is resistant to high temperature annealing in oxygen environments. When used with an underlying Ta or TaN layer, the resulting conductive barrier also suppresses to diffusion of Ir into any underlying Si substrates. As a result, Ir silicide products are not formed, which degrade the electrode interface characteristics. That is, the Ir combination film remains conductive, not peeling or forming hillocks, during high temperature annealing processes, even in oxygen. A method for forming an Ir composite film barrier layer and Ir composite film ferroelectric electrode are also provided.

摘要翻译： 已经提供了可用于形成铁电电容器的电极的Ir组合膜。 组合膜包括钽和氧，以及铱。 Ir组合膜有效防止氧气扩散，并且在氧气环境中耐高温退火。 当与下面的Ta或TaN层一起使用时，所得到的导电屏障还抑制Ir扩散到任何下面的Si衬底中。 结果，不形成铱硅化物产物，这降低了电极界面的特性。 也就是说，即使在氧气中，Ir组合膜在高温退火过程中仍保持导电性，不会剥离或形成小丘。 还提供了形成Ir复合膜阻挡层和Ir复合膜铁电电极的方法。

公开(公告)号：US06303502B1

公开(公告)日：2001-10-16

申请号：US09588940

申请日：2000-06-06

申请人： Sheng Teng Hsu ,  David R. Evans ,  Tingkai Li ,  Jer-shen Maa ,  Wei-Wei Zhuang

发明人： Sheng Teng Hsu ,  David R. Evans ,  Tingkai Li ,  Jer-shen Maa ,  Wei-Wei Zhuang

IPC分类号： H01L2144

CPC分类号： H01L21/28291 ,  H01L29/78391

摘要： A method of fabricating a one-transistor memory includes, on a single crystal silicon substrate, depositing a bottom electrode structure on a gate oxide layer; implanting ions to form a source region and a drain region and activating the implanted ions spin coating the structure with a first ferroelectric layer; depositing a second ferroelectric layer; and annealing the structure to provide a c-axis ferroelectric orientation.

摘要翻译： 制造单晶体管存储器的方法包括在单晶硅衬底上，在栅氧化层上沉积底电极结构; 注入离子以形成源极区域和漏极区域并激活注入的离子旋转涂覆第一铁电层的结构; 沉积第二铁电层; 并退火该结构以提供c轴铁电取向。