公开(公告)号：US20240347585A1

公开(公告)日：2024-10-17

申请号：US18753743

申请日：2024-06-25

Applicant: MaxPower Semiconductor, Inc.

Inventor： Jun Zeng ,  Mohamed Darwish ,  Shih-Tzung Su

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0619 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66712 ,  H01L29/7813

Abstract: A vertical trench MOSFET is formed with deep P-shield regions below portions of each gate trench. The deep P-shield regions are effectively downward extensions of the P-body/well, and are electrically coupled to the top source electrode. The P-shield regions abut the bottom portions and lower sides of the gate trenches, so that those small portions of the gate trench do not create N-channels and do not conduct current. Accordingly, each trench comprises an active gate portion that creates an N-channel and a small non-active portion that abuts the P-shield regions. The spacing of the P-shield regions along each gate trench is selected to achieve the desired electric field spreading to protect the gate oxide from punch-through. No field plate trenches are needed to be formed in the active area of the MOSFET. The deep P-shield regions may be formed in trench areas that are deeper than the active gate trench areas.

公开(公告)号：US20240339494A1

公开(公告)日：2024-10-10

申请号：US18625100

申请日：2024-04-02

Applicant: MaxPower Semiconductor, Inc.

Inventor： Mohamed Darwish ,  Jun Zeng

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0611 ,  H01L29/7813 ,  H01L29/7832

Abstract: A vertical MOSFET has an N-type drift layer over an N+ substrate. A horizontal JFET layer overlies the drift layer, where the JFET layer has P-type gate regions and N-type channel regions. A first N-type layer overlies the JFET layer. A P-type well layer overlies the first N-type layer. Gate trenches are formed through the P-type well layer and into the first N-type layer. N-type source regions abut the top areas of the gate trenches, and a source electrode contacts the source regions. The JFET N-type channel regions are generally directly below the gate trenches for conducting a vertical current when the MOSFET is in an on state. The source electrode is electrically connected to the JFET P-type gate regions via a deep P-type contact region. The JFET N-type channel regions pinch off during short circuit high current conditions to limit drain current.

公开(公告)号：US11316021B2

公开(公告)日：2022-04-26

申请号：US16991935

申请日：2020-08-12

Applicant: MaxPower Semiconductor Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng ,  Richard A. Blanchard

IPC: H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/06

Abstract: A vertical transistor structure in which a recessed field plate trench surrounds multiple adjacent gate electrodes. Thus the specific on-state conductance is increased, since the ratio of recessed field plate area to channel area is reduced. Various versions use two, three, or more distinct gate electrodes within the interior of a single RFP or RSFP trench's layout.

公开(公告)号：US20180337230A1

公开(公告)日：2018-11-22

申请号：US16014635

申请日：2018-06-21

Applicant: MaxPower Semiconductor Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng ,  Richard A. Blanchard

IPC: H01L29/06 ,  H01L29/861 ,  H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L21/265

CPC classification number: H01L29/0611 ,  H01L21/26586 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0873 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8611

Abstract: Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region.

公开(公告)号：US10128353B2

公开(公告)日：2018-11-13

申请号：US15809863

申请日：2017-11-10

Applicant: MaxPower Semiconductor Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng ,  Richard A. Blanchard

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/16 ,  H01L29/36 ,  H01L29/739 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08

Abstract: Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.

公开(公告)号：US20180261666A1

公开(公告)日：2018-09-13

申请号：US15894811

申请日：2018-02-12

Applicant: MaxPower Semiconductor Inc.

Inventor： Jun Zeng ,  Mohamed N. Darwish ,  Wenfang Du ,  Richard A. Blanchard ,  Kui Pu ,  Shih-Tzung Su

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/7397 ,  H01L29/7813

Abstract: In one embodiment, a power MOSFET or IGBT cell includes an N-type drift region grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed over the drift region. A P-well is formed over the N-type layer, and an N+ source/emitter region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into a trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction in the N-type layer along the sidewalls of the trench to reduce on-resistance. A vertical shield field plate is also in the trench and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. Floating P-islands in the N-type drift region increase breakdown voltage and reduce the saturation current.

公开(公告)号：US20170365683A1

公开(公告)日：2017-12-21

申请号：US15676792

申请日：2017-08-14

Applicant: MaxPower Semiconductor, Inc.

Inventor： Richard A. Blanchard ,  Mohamed N. Darwish ,  Jun Zeng

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/16 ,  H01L21/265 ,  H01L21/04 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L29/66068 ,  H01L21/047 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2822 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7813

Abstract: In one embodiment, a power MOSFET vertically conducts current. A bottom electrode may be connected to a positive voltage, and a top electrode may be connected to a low voltage, such as a load connected to ground. A gate and/or a field plate, such as polysilicon, is within a trench. The trench has a tapered oxide layer insulating the polysilicon from the silicon walls. The oxide is much thicker near the bottom of the trench than near the top to increase the breakdown voltage. The tapered oxide is formed by implanting nitrogen into the trench walls to form a tapered nitrogen dopant concentration. This forms a tapered silicon nitride layer after an anneal. The tapered silicon nitride variably inhibits oxide growth in a subsequent oxidation step.

公开(公告)号：US09761702B2

公开(公告)日：2017-09-12

申请号：US15240831

申请日：2016-08-18

Applicant: MaxPower Semiconductor, Inc.

Inventor： Jun Zeng ,  Mohamed N. Darwish ,  Kui Pu ,  Shih-Tzung Su

IPC: H01L29/739 ,  H01L29/08 ,  H01L29/40 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

Abstract: In one embodiment, a power MOSFET cell includes an N+ silicon substrate having a drain electrode. An N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed along with a trench having sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into the trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. A buried layer and sinker enable the use of a topside drain electrode.

公开(公告)号：US09385227B2

公开(公告)日：2016-07-05

申请号：US14027873

申请日：2013-09-16

Applicant: MaxPower Semiconductor, Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7816 ,  H01L21/26586 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7835 ,  H01L29/78624 ,  H03K17/04106

Abstract: Lateral power devices where immobile electrostatic charge is emplaced in dielectric material adjoining the drift region. A shield gate is interposed between the gate electrode and the drain, to reduce the Miller charge. In some embodiments the gate electrode is a trench gate, and in such cases the shield electrode too is preferably vertically extended.

公开(公告)号：US20160064497A1

公开(公告)日：2016-03-03

申请号：US14840744

申请日：2015-08-31

Applicant: MaxPower Semiconductor Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng

IPC: H01L29/40 ,  H03K17/687 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/16

CPC classification number: H01L29/7811 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0856 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/404 ,  H01L29/407 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/7813 ,  H01L29/7823 ,  H01L29/7827 ,  H01L29/7835 ,  H03K17/687

Abstract: N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate).

Abstract translation: 其中绝缘场板耦合到漂移区的N沟道功率半导体器件，并且固定静电电荷也存在于漂移区和场板周围的绝缘体之间的界面处。 除了在漏极区附近发生的电压降（由于场板的存在）外，静电电荷还允许在源极区域附近发生OFF状态电压降。