Process gas focusing apparatus and method
    21.
    发明授权
    Process gas focusing apparatus and method 失效
    工艺气体聚焦装置及方法

    公开(公告)号:US5891348A

    公开(公告)日:1999-04-06

    申请号:US592821

    申请日:1996-01-26

    摘要: An apparatus (20) for uniformly processing substrates (25) having a surface with a center (80) and a peripheral edge (85). The apparatus (20) comprises (i) a process chamber (30) having a gas distributor (55) for distributing process gas in the process chamber (30); (ii) a support (75) for supporting a substrate (25) in the process chamber (30); (iii) a plasma generator for forming a plasma from the process gas in the process chamber (30); and (iv) a focus ring (90) in the process chamber (30). The focus ring (90) comprises (a) a wall (95) surrounding the substrate (25) to substantially contain the plasma on the substrate surface, and (b) a channel (100) in the wall (95). The channel (100) has an inlet (105) adjacent to, and extending substantially continuously around the peripheral edge (85) of the substrate surface. The inlet (105) of the channel (100) has a width w sized to allow a sufficient amount of process gas to flow into the channel (100) to maintain substantially equal processing rates at the center (80) and peripheral edge (85) of the substrate surface.

    摘要翻译: 一种用于均匀地处理具有中心(80)和周缘(85)的表面的基板(25)的装置(20)。 设备(20)包括(i)具有用于在处理室(30)中分配处理气体的气体分配器(55)的处理室(30)。 (ii)用于在处理室(30)中支撑衬底(25)的支撑件(75); (iii)用于在所述处理室(30)中从所述处理气体形成等离子体的等离子体发生器; 和(iv)处理室(30)中的聚焦环(90)。 聚焦环(90)包括(a)围绕基底(25)以在基底表面上基本上包含等离子体的壁(95),和(b)壁(95)中的通道(100)。 通道(100)具有与衬底表面的周边边缘(85)相邻并且基本上连续地延伸的入口(105)。 通道(100)的入口(105)具有宽度w,其尺寸允许足够量的处理气体流入通道(100),以在中心(80)和外围边缘(85)处保持基本上相等的处理速率, 的基板表面。

    RF plasma reactor with cleaning electrode for cleaning during processing
of semiconductor wafers
    22.
    发明授权
    RF plasma reactor with cleaning electrode for cleaning during processing of semiconductor wafers 失效
    RF等离子体反应器,其具有用于在半导体晶片的处理期间进行清洁的清洁电极

    公开(公告)号:US5817534A

    公开(公告)日:1998-10-06

    申请号:US567376

    申请日:1995-12-04

    摘要: The invention is carried out in a plasma reactor for processing a semiconductor wafer, the plasma reactor having a chamber for containing a processing gas and having a conductor connected to an RF power source for coupling RF power into the reactor chamber to generate from the processing gas a plasma inside the chamber, the chamber containing at least one surface exposed toward the plasma and susceptible to contamination by particles produced during processing of the wafer, the invention being carried out by promoting, during processing of the wafer, bombarding of particles from the plasma onto the one surface to remove therefrom contaminants deposited during processing of the wafer. Such promoting of bombarding is carried out by providing an RF power supply and coupling, during processing of the wafer, RF power from the supply to the one surface. The coupling may be performed by a capacitive cleaning electrode adjacent the one surface, the capacitive cleaning electrode connected to the RF power supply. The capacitive cleaning electrode preferably is disposed on a side of the one surface opposite the plasma so as to be protected from contact with the plasma. Alternatively, the coupling may be carried out by a direct electrical connection from the RF power supply to the one surface.

    摘要翻译: 本发明在用于处理半导体晶片的等离子体反应器中进行,等离子体反应器具有用于容纳处理气体的室,并具有连接到RF电源的导体,用于将RF功率耦合到反应器室中以从处理气体产生 腔室内的等离子体,该腔室包含至少一个暴露于等离子体的表面并容易受到在晶片加工期间产生的颗粒的污染,本发明通过在晶片加工期间促进从等离子体中轰击颗粒而进行 在一个表面上去除在晶片加工期间沉积的污染物。 通过在晶片的处理期间提供RF电源和耦合来进行轰击的这种促进是从电源到单个表面的RF功率。 耦合可以通过与一个表面相邻的电容清洁电极,电容清洁电极连接到RF电源来进行。 电容式清洁电极优选地设置在与等离子体相对的一个表面的一侧,以便被保护而不与等离子体接触。 或者,耦合可以通过从RF电源到一个表面的直接电连接来执行。

    Non-permeable substrate carrier for electroplating
    23.
    发明授权
    Non-permeable substrate carrier for electroplating 有权
    用于电镀的不可渗透的基底载体

    公开(公告)号:US08317987B2

    公开(公告)日:2012-11-27

    申请号:US12889219

    申请日:2010-09-23

    IPC分类号: C25B9/02

    摘要: One embodiment relates to a substrate carrier for use in electroplating a plurality of substrates. The substrate carrier comprises a non-conductive carrier body on which the substrates are to be held. Electrically-conductive lines are embedded within the carrier body, and a plurality of contact clips are coupled to the electrically-conductive lines embedded within the carrier body. The contact clips hold the substrates in place and electrically couple the substrates to the electrically-conductive lines. The non-conductive carrier body is continuous so as to be impermeable to flow of electroplating solution through the non-conductive carrier body. Other embodiments, aspects and features are also disclosed.

    摘要翻译: 一个实施例涉及用于电镀多个基板的基板载体。 衬底载体包括其上将保持衬底的非导电载体。 导电线嵌入载体主体内,并且多个接触夹被耦合到嵌入载体主体内的导电线。 接触夹将基板固定在适当位置,并将基板电耦合到导电线。 非导电载体主体是连续的,以便不可渗透通过非导电载体的电镀溶液流动。 还公开了其它实施例,方面和特征。

    System level in-situ integrated dielectric etch process particularly useful for copper dual damascene
    25.
    发明授权
    System level in-situ integrated dielectric etch process particularly useful for copper dual damascene 失效
    系统级原位集成电介质蚀刻工艺特别适用于铜双镶嵌

    公开(公告)号:US06949203B2

    公开(公告)日:2005-09-27

    申请号:US10379439

    申请日:2003-03-03

    摘要: An integrated in situ etch process performed in a multichamber substrate processing system having first and second etching chambers. In one embodiment the first chamber includes an interior surface that has been roughened to at least 100 Ra and the second chamber includes an interior surface that has a roughness of less than about 32 Ra. The process includes transferring a substrate having formed thereon in a downward direction a patterned photoresist mask, a dielectric layer, a barrier layer and a feature in the substrate to be contacted into the first chamber where the dielectric layer is etched in a process that encourages polymer formation over the roughened interior surface of the chamber. The substrate is then transferred from the first chamber to the second chamber under vacuum conditions and, in the second chamber, is exposed to a reactive plasma such as oxygen to strip away the photoresist mask deposited over the substrate. After the photoresist mask is stripped, the barrier layer is etched through to the feature to be contacted in the second chamber of the multichamber substrate processing system using a process that discourages polymer formation over the relatively smooth interior surface of the second chamber. All three etching steps are performed in a system level in situ process so that the substrate is not exposed to an ambient between steps. In some embodiments the interior surface of the first chamber has a roughness between 100 and 200 Ra and in other embodiments the roughness of the first chamber's interior surface is between 110 and 160 Ra.

    摘要翻译: 在具有第一和第二蚀刻室的多室衬底处理系统中执行的集成原位蚀刻工艺。 在一个实施例中,第一室包括已经被粗糙化至少100个的内表面,而第二室包括具有小于约32μm的粗糙度的内表面, / SUB>。 该方法包括在向下的方向上转移其上形成有图案的光致抗蚀剂掩模,电介质层,阻挡层和衬底中的特征的衬底,以接触第一室,其中介电层被刻蚀在鼓励聚合物的过程中 在室的粗糙内表面上形成。 然后在真空条件下将衬底从第一室转移到第二室,并且在第二室中暴露于诸如氧的反应性等离子体以剥离沉积在衬底上的光致抗蚀剂掩模。 在光致抗蚀剂掩模被剥离之后,通过阻止在第二室的相对光滑的内表面上聚合物形成的工艺,阻挡层被蚀刻到多室基板处理系统的第二室中以接触的特征。 所有三个蚀刻步骤都是在系统级原位工艺中进行的,因此基板不会在台阶之间暴露于环境中。 在一些实施例中,第一室的内表面具有在100和200之间的粗糙度,而在其它实施例中,第一室的内表面的粗糙度在110和160之间, SUB>。

    Method for etching low k dielectrics
    26.
    发明授权
    Method for etching low k dielectrics 失效
    蚀刻低k电介质的方法

    公开(公告)号:US06547977B1

    公开(公告)日:2003-04-15

    申请号:US09610915

    申请日:2000-07-05

    IPC分类号: C03C1500

    CPC分类号: H01L21/31138

    摘要: The present disclosure pertains to a method for plasma etching of low k materials, particularly polymeric-based low k materials. Preferably the polymeric-based materials are organic-based materials. The method employs an etchant plasma where the major etchant species are generated from a halogen other than fluorine and oxygen. The preferred halogen is chlorine. The volumetric (flow rate) ratio of the halogen:oxygen in the plasma source gas ranges from about 1:20 to about 20:1. The atomic ratio of the halogen:oxygen preferably falls within the range from about 1:20 to about 20:1. When the halogen is chlorine, the preferred atomic ratio of chlorine:oxygen ranges from about 1:10 to about 5:1. When this atomic ratio of chlorine:oxygen is used, the etch selectivity for the low k material over adjacent oxygen-comprising or nitrogen-comprising layers is advantageous, typically in excess of about 10:1. The plasma source gas may contain additives in an amount of 15% or less by volume which are designed to improve selectivity for the low k dielectric over an adjacent material, to provide a better etch profile, or to provide better critical dimension control, for example. When the additive contains fluorine, the amount of the additive is such that residual chlorine on the etched surface of the low k material comprises less than 5 atomic %.

    摘要翻译: 本公开涉及用于等离子体蚀刻低k材料,特别是基于聚合物的低k材料的方法。 优选地,基于聚合物的材料是有机基材料。 该方法采用蚀刻剂等离子体,其中主要蚀刻剂物质由除氟和氧之外的卤素产生。 优选的卤素是氯。 等离子体源气体中的卤素:氧的体积(流速)比为约1:20至约20:1。 卤素:氧的原子比优选在约1:20至约20:1的范围内。 当卤素为氯时,氯:氧的优选原子比范围为约1:10至约5:1。 当使用氯原子的氧原子比时,低k材料在相邻的含氧或含氮层上的蚀刻选择性是有利的,通常超过约10:1。 等离子体源气体可以含有体积的15%或更少的添加剂,其被设计成提高相邻材料上的低k电介质的选择性,以提供更好的蚀刻轮廓,或提供更好的临界尺寸控制,例如 。 当添加剂含氟时,添加剂的量使得低k材料的蚀刻表面上的残留氯含量小于5原子%。

    Post-etch treatment of plasma-etched feature surfaces to prevent
corrosion
    27.
    发明授权
    Post-etch treatment of plasma-etched feature surfaces to prevent corrosion 失效
    蚀刻后处理等离子蚀刻特征表面以防止腐蚀

    公开(公告)号:US6153530A

    公开(公告)日:2000-11-28

    申请号:US270286

    申请日:1999-03-16

    CPC分类号: H01L21/02071

    摘要: Disclosed herein is a post-etch treatment for plasma etched metal-comprising features in semiconductor devices. The post-etch treatment significantly reduces or eliminates surface corrosion of the etched metal-comprising feature. It is particularly important to prevent the formation of moisture on the surface of the feature surface prior to an affirmative treatment to remove corrosion-causing contaminants from the feature surface. Avoidance of moisture formation is assisted by use of a high vacuum; use of an inert, moisture-free purge gas; and by maintaining the substrate at a sufficiently high temperature to volatilize moisture. The affirmative post-etch treatment utilizes a plasma to expose the etched metal-comprising feature to sufficient hydrogen which is in a kinetic state permitting reaction with residual halogen-comprising residues on the etched surface, while maintaining the etched feature surface at a temperature which supports volatilization of the byproducts of a reaction between the active hydrogen species and the halogen-comprising residues. For an etched copper surface, if moisture forms on the etched surface prior to an affirmative treatment to remove corrosion-causing contaminants, it is very important to avoid contact of the etched surface with pollutants which are capable of forming copper carbonates and/or copper sulfates.

    摘要翻译: 本文公开了用于半导体器件中等离子体蚀刻金属的特征的后蚀刻处理。 蚀刻后处理显着地减少或消除了蚀刻的金属包含特征的表面腐蚀。 特别重要的是在肯定处理之前防止在特征表面的表面上形成湿气以从特征表面除去腐蚀性污染物。 通过使用高真空来辅助避免水分形成; 使用惰性,无湿气的吹扫气体; 并且通过将基底保持在足够高的温度以使水分挥发。 肯定的后蚀刻处理利用等离子体将含蚀刻金属的特征暴露于足够的氢气,该氢气处于动态状态,允许与蚀刻表面上的残留的含卤素残留物反应,同时将蚀刻的特征表面保持在支持 活性氢物质与含卤素残基之间的反应的副产物挥发。 对于蚀刻的铜表面,如果在进行肯定处理以除去腐蚀性污染物之前在蚀刻表面上形成水分,则避免蚀刻表面与能够形成碳酸铜和/或硫酸铜的污染物接触是非常重要的 。

    Method of etching patterned layers useful as masking during subsequent
etching or for damascene structures
    28.
    发明授权
    Method of etching patterned layers useful as masking during subsequent etching or for damascene structures 失效
    在随后的蚀刻或镶嵌结构期间蚀刻用作掩模的图案化层的方法

    公开(公告)号:US6080529A

    公开(公告)日:2000-06-27

    申请号:US174763

    申请日:1998-10-19

    摘要: A first embodiment of the present invention pertains to a method of patterning a semiconductor device conductive feature while permitting easy removal of any residual masking layer which remains after completion of the etching process. A multi-layered masking structure is used which includes a layer of high-temperature organic-based masking material overlaid by either a patterned layer of inorganic masking material or by a layer of patterned high-temperature imageable organic masking material. The inorganic masking material is used to transfer a pattern to the high-temperature organic-based masking material and is then removed. The high-temperature organic-based masking material is used to transfer the pattern and then may be removed if desired. This method is also useful in the pattern etching of aluminum, even though aluminum can be etched at lower temperatures. A second embodiment of the present invention pertains to a specialized etch chemistry useful in the patterning of organic polymeric layers such as low k dielectrics, or other organic polymeric interfacial layers. This etch chemistry is useful for mask opening during the etch of a conductive layer or is useful in etching damascene structures where a metal fill layer is applied over the surface of a patterned organic-based dielectric layer. The etch chemistry provides for the use of etchant plasma species which minimize oxygen, fluorine, chlorine, and bromine content.

    摘要翻译: 本发明的第一实施例涉及一种图案化半导体器件导电特征的方法,同时允许容易地去除在蚀刻工艺完成之后保留的任何残留掩模层。 使用多层掩模结构,其包括由无机掩模材料的图案化层或由图案化的高温可成像有机掩蔽材料层覆盖的高温有机基掩蔽材料层。 无机掩模材料用于将图案转印到高温有机基掩蔽材料上,然后除去。 高温有机基掩蔽材料用于转移图案,然后如果需要可以去除。 这种方法在铝的图案蚀刻中也是有用的,即使在较低温度下可以蚀刻铝。 本发明的第二个实施方案涉及可用于图案化有机聚合物层如低k电介质或其它有机聚合物界面层的专用蚀刻化学物质。 该蚀刻化学物质可用于在导电层的蚀刻过程中的掩模开口,或者可用于蚀刻镶嵌结构,其中金属填充层施加在图案化有机基介质层的表面上。 蚀刻化学提供了使氧化物,氟,氯和溴含量最小化的蚀刻剂等离子体物质的使用。

    Patterned copper etch for micron and submicron features, using enhanced
physical bombardment
    29.
    发明授权
    Patterned copper etch for micron and submicron features, using enhanced physical bombardment 失效
    用于微米和亚微米特征的图案化铜蚀刻,使用增强的物理轰击

    公开(公告)号:US6010603A

    公开(公告)日:2000-01-04

    申请号:US891410

    申请日:1997-07-09

    摘要: Copper can be pattern etched at acceptable rates and with selectivity over adjacent materials using an etch process which utilizes a solely physical process which we have termed "enhanced physical bombardment". Enhanced physical bombardment requires an increase in ion density and/or an increase in ion energy of ionized species which strike the substrate surface. To assist in the removal of excited copper atoms from the surface being etched, the power to the ion generation source and/or the substrate offset bias source may be pulsed. In addition, when the bombarding ions are supplied from a remote source, the supply of these ions may be pulsed. Further, thermal phoresis may be used by maintaining a substrate temperature which is higher than the temperature of a surface in the etch chamber. It is also possible to use a chemically reactive species in combination with the physical ion bombardment without causing copper corrosion problems, so long as the concentration of the chemically reactive ion component is sufficiently low that the etching is carried out in a physical bombardment dominated etch regime.

    摘要翻译: 铜可以以可接受的速率进行图案蚀刻,并且使用使用仅称为“增强物理轰击”的物理过程的蚀刻工艺对相邻材料具有选择性。 增强的物理轰击需要离子密度的增加和/或离子化物质的离子能量的增加,这些物质撞击到基底表面。 为了帮助从被蚀刻的表面去除激发的铜原子,离子产生源和/或衬底偏置偏置源的功率可以是脉冲的。 此外,当从远程源供应轰击离子时,这些离子的供应可以是脉冲的。 此外,可以通过保持高于蚀刻室中的表面的温度的衬底温度来使用热电泳。 只要化学反应离子组分的浓度足够低以致蚀刻在物理轰击主导的蚀刻状态下进行,也可以将化学反应物质与物理离子轰击结合使用而不引起铜腐蚀问题 。

    RF plasma reactor with hybrid conductor and multi-radius dome ceiling
    30.
    发明授权
    RF plasma reactor with hybrid conductor and multi-radius dome ceiling 失效
    射频等离子体反应器与混合导体和多半圆顶天花板

    公开(公告)号:US5777289A

    公开(公告)日:1998-07-07

    申请号:US597445

    申请日:1996-02-02

    CPC分类号: H01J37/321

    摘要: An inductively coupled RF plasma reactor for processing semiconductor wafer includes a reactor chamber having a side wall and a ceiling, a wafer pedestal for supporting the wafer in the chamber, an RF power source, apparatus for introducing a processing gas into the reactor chamber, and a coil inductor adjacent the reactor chamber connected to the RF power source, the coil inductor including (a) a side section facing a portion of the side wall and including a bottom winding and a top winding, the top winding being at a height corresponding at least approximately to a top height of the ceiling, and (b) a top section extending radially inwardly from the top winding of the side section so as to overlie at least a substantial portion of the ceiling. The present invention adheres to an optimized coil-dome geometry including a particular dome apex height range relative to the dome base and a particular wafer position range relative to the dome apex.

    摘要翻译: 用于处理半导体晶片的感应耦合RF等离子体反应器包括具有侧壁和天花板的反应室,用于将晶片支撑在室中的晶片基座,RF电源,将处理气体引入反应室的装置,以及 与所述反应室相邻的线圈电感器,所述线圈电感器连接到所述RF电源,所述线圈电感器包括(a)面向所述侧壁的一部分并包括底部绕组和顶部绕组的侧面部分,所述顶部绕组的高度对应于 至少约至顶部的顶部高度,以及(b)从侧部的顶部绕组径向向内延伸的顶部部分,以覆盖至少大部分天花板。 本发明遵循优化的线圈 - 圆顶几何形状,其包括相对于圆顶基座的特定圆顶顶部高度范围和相对于圆顶顶点的特定晶片位置范围。