Patent search ap:("Micron Technology Page Inc.") AND inv:"Aibin Yu"

21.

发明授权
Semiconductor die assemblies with heat sink and associated systems and methods 有权

公开(公告)号：US09716019B2

公开(公告)日：2017-07-25

申请号：US15134788

申请日：2016-04-21

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou , Zhaohui Ma , Aibin Yu

IPC: H01L21/44 , H01L21/48 , H01L23/373 , H01L25/065 , H01L25/00 , H01L23/433 , H01L21/56 , H01L23/00 , H01L25/18 , H01L23/31 , H01L23/367 , H01L21/78

CPC classification number: H01L21/4882 , H01L21/4878 , H01L21/561 , H01L21/565 , H01L21/568 , H01L21/78 , H01L23/3121 , H01L23/367 , H01L23/3731 , H01L23/3738 , H01L23/4334 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/06181 , H01L2224/13147 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2224/17519 , H01L2224/29191 , H01L2224/293 , H01L2224/29393 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/73204 , H01L2224/73253 , H01L2224/81 , H01L2224/83 , H01L2224/83104 , H01L2224/92125 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06568 , H01L2225/06589 , H01L2924/00 , H01L2924/00014 , H01L2924/01006 , H01L2924/01014 , H01L2924/014 , H01L2924/05432 , H01L2924/15311 , H01L2924/15738 , H01L2924/15787

Abstract: Semiconductor die assemblies with heat sinks are disclosed herein. In one embodiment, a semiconductor die assembly includes a stack of semiconductor dies and a mold material surrounding at least a portion of the stack of semiconductor dies. A heat sink is disposed on the stack of semiconductor dies and adjacent the mold material. The heat sink includes an exposed surface and a plurality of heat transfer features along the exposed surface that are configured to increase an exposed surface area compared to a planar surface.

22.

发明授权
Methods of processing wafer-level assemblies to reduce warpage, and related assemblies 有权
Title translation: 处理晶圆级组件以减少翘曲的方法和相关组件

公开(公告)号：US09589933B2

公开(公告)日：2017-03-07

申请号：US14312147

申请日：2014-06-23

Applicant: Micron Technology, Inc.

Inventor： Aibin Yu , Wei Zhou , Zhaohui Ma , Bret K. Street

IPC: H01L21/78 , H01L25/065

CPC classification number: H01L23/562 , H01L21/561 , H01L23/544 , H01L25/0657 , H01L2223/5446 , H01L2924/0002 , H01L2924/00

Abstract: Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in streets and at least surrounding stacks of semiconductor dice located on a wafer. Wafer-level methods of preparing semiconductor devices may involve attaching a wafer to a carrier substrate and forming stacks of laterally spaced semiconductor dice on die locations of the wafer. Molding material may be disposed over the die stacks on a surface of the wafer to at least surround the stacks of semiconductor dice with the molding material. Grooves may be formed in the molding material by partially cutting through the molding material between at least some of the stacks of semiconductor dice along streets between the die stacks. The resulting wafer-level assembly may then, when exposed to elevated temperatures during, for example, debonding the wafer from a carrier, exhibit reduced propensity for warping.

Abstract translation: 处理半导体器件的晶片级方法可以包括部分地通过模制材料形成凹槽，模制材料位于街道上，并且至少围绕位于晶片上的半导体芯片堆叠。制备半导体器件的晶片级方法可以包括将晶片附着到载体衬底并且在晶片的芯片位置上形成横向间隔开的半导体晶片的堆叠。模制材料可以设置在晶片的表面上的模具堆叠上，以至少用模制材料围绕半导体晶片的堆叠。可以通过在模具堆叠之间沿着街道的半导体芯片的至少一些堆叠之间部分地切割模制材料，而在模制材料中形成凹槽。然后，当例如在晶片脱离载体时暴露于升高的温度时，所得到的晶片级组件可能表现出降低的翘曲倾向。

23.

发明授权
Methods of protecting peripheries of in-process semiconductor wafers and related in-process wafers and systems 有权
Title translation: 保护工艺中半导体晶圆和相关工艺中晶片和系统的周边的方法

公开(公告)号：US09337064B2

公开(公告)日：2016-05-10

申请号：US14485973

申请日：2014-09-15

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou , Aibin Yu , Zhaohui Ma

IPC: H01L23/495 , H01L23/58 , H01L21/00 , H01L21/56 , H01L21/311 , H01L21/306 , H01L21/324 , H01L23/31

CPC classification number: H01L21/565 , H01L21/30604 , H01L21/31111 , H01L21/324 , H01L21/56 , H01L21/561 , H01L21/568 , H01L23/3157 , H01L23/562 , H01L2924/0002 , H01L2924/00

Abstract: Methods of processing semiconductor wafers may involve, for example, encapsulating an active surface and each side surface of a wafer of semiconductor material, a plurality of semiconductor devices located on the active surface of the wafer, an exposed side surface of an adhesive material located on a back side surface of the wafer, and at least a portion of a side surface of a carrier substrate secured to the wafer by the adhesive material in an encapsulation material. At least a portion of the side surface of the adhesive material may be exposed by removing at least a portion of the encapsulation material. The carrier substrate may be detached from the wafer. Processing systems and in-process semiconductor wafers are also disclosed.

Abstract translation: 处理半导体晶片的方法可以包括例如封装半导体材料晶片的活性表面和每个侧表面，位于晶片的有效表面上的多个半导体器件，位于晶片的背面表面和载体基板的侧表面的至少一部分通过胶粘材料固定在晶片上。粘合剂材料的侧表面的至少一部分可以通过去除包封材料的至少一部分而暴露。载体衬底可以从晶片分离。还公开了处理系统和工艺中半导体晶片。

24.

发明申请
METHODS OF PROCESSING WAFER-LEVEL ASSEMBLIES TO REDUCE WARPAGE, AND RELATED ASSEMBLIES 有权
Title translation: 加工水平组合减少威胁的方法和相关组织

公开(公告)号：US20150371969A1

公开(公告)日：2015-12-24

申请号：US14312147

申请日：2014-06-23

Applicant: Micron Technology, Inc.

Inventor： Aibin Yu , Wei Zhou , Zhaohui Ma , Bret K. Street

IPC: H01L25/065 , H01L21/77

CPC classification number: H01L23/562 , H01L21/561 , H01L23/544 , H01L25/0657 , H01L2223/5446 , H01L2924/0002 , H01L2924/00

Abstract: Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in streets and at least surrounding stacks of semiconductor dice located on a wafer. Wafer-level methods of preparing semiconductor devices may involve attaching a wafer to a carrier substrate and forming stacks of laterally spaced semiconductor dice on die locations of the wafer. Molding material may be disposed over the die stacks on a surface of the wafer to at least surround the stacks of semiconductor dice with the molding material. Grooves may be formed in the molding material by partially cutting through the molding material between at least some of the stacks of semiconductor dice along streets between the die stacks. The resulting wafer-level assembly may then, when exposed to elevated temperatures during, for example, debonding the wafer from a carrier, exhibit reduced propensity for warping.

Abstract translation: 处理半导体器件的晶片级方法可以包括部分地通过模制材料形成凹槽，模制材料位于街道上，并且至少围绕位于晶片上的半导体芯片堆叠。制备半导体器件的晶片级方法可以包括将晶片附着到载体衬底并且在晶片的芯片位置上形成横向间隔开的半导体晶片的堆叠。模制材料可以设置在晶片的表面上的模具堆叠上，以至少用模制材料围绕半导体晶片的堆叠。可以通过在模具堆叠之间沿着街道的半导体芯片的至少一些堆叠之间部分地切割模制材料，而在模制材料中形成凹槽。然后，当例如在晶片脱离载体时暴露于升高的温度时，所得到的晶片级组件可能表现出降低的翘曲倾向。

25.

发明公开
SILICON SPACERS WITH IMPROVED ADHESION AND SEMICONDUCTOR DEVICE ASSEMBLIES INCORPORATING THE SAME 审中-公开

公开(公告)号：US20230268263A1

公开(公告)日：2023-08-24

申请号：US17676037

申请日：2022-02-18

Applicant: Micron Technology, Inc.

Inventor： Aibin Yu , Yee Chon Chin

IPC: H01L23/498 , H01L21/56 , H01L25/065 , H01L23/31 , H01L21/48 , H01L25/00

CPC classification number: H01L23/49838 , H01L21/565 , H01L25/0652 , H01L23/3121 , H01L23/3142 , H01L21/4857 , H01L25/50 , H01L2224/48225 , H01L24/48

Abstract: A semiconductor device assembly is provided. The semiconductor device assembly includes a package substrate and a silicon spacer disposed on an upper surface of the substrate, the silicon spacer having a plurality of trenches extending into the silicon spacer from a top surface thereof. The semiconductor device assembly further includes one or more semiconductor devices disposed over the silicon spacer. Moreover, the semiconductor device assembly includes an encapsulant material at least partially encapsulating the one or more semiconductor devices and the package substrate, the encapsulant material at least partially filling the plurality of trenches of the silicon spacer.

26.

发明授权
Semiconductor devices comprising protected side surfaces and related methods 有权

公开(公告)号：US10312226B2

公开(公告)日：2019-06-04

申请号：US15728043

申请日：2017-10-09

Applicant: Micron Technology, Inc.

Inventor： Zhaohui Ma , Wei Zhou , Chee Chung So , Soo Loo Ang , Aibin Yu

IPC: H01L25/18 , H01L25/065 , H01L25/00 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/544 , H01L21/683 , H01L21/78

Abstract: Methods of protecting semiconductor devices may involve cutting partially through a thickness of a semiconductor wafer to form trenches between stacks of semiconductor dice on regions of integrated circuitry of the semiconductor wafer. A protective material may be dispensed into the trenches and to a level at least substantially the same as a height of the stacks of semiconductor dice. Material of the semiconductor wafer may be removed from a back side thereof at least to a depth sufficient to expose the protective material in the trenches. A remaining thickness of the protective material between the stacks of semiconductor dice may be cut through.

27.

发明授权
Semiconductor die assemblies with heat sink and associated systems and methods 有权

公开(公告)号：US10153178B2

公开(公告)日：2018-12-11

申请号：US15655736

申请日：2017-07-20

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou , Zhaohui Ma , Aibin Yu

IPC: H01L23/10 , H01L21/48 , H01L23/373 , H01L25/065 , H01L25/00 , H01L23/433 , H01L21/56 , H01L23/00 , H01L25/18 , H01L23/31 , H01L23/367 , H01L21/78

Abstract: Semiconductor die assemblies with heat sinks are disclosed herein. In one embodiment, a semiconductor die assembly includes a stack of semiconductor dies and a mold material surrounding at least a portion of the stack of semiconductor dies. A heat sink is disposed on the stack of semiconductor dies and adjacent the mold material. The heat sink includes an exposed surface and a plurality of heat transfer features along the exposed surface that are configured to increase an exposed surface area compared to a planar surface.