公开(公告)号：US10601313B2

公开(公告)日：2020-03-24

申请号：US16430761

申请日：2019-06-04

Applicant: Micron Technology, Inc.

Inventor： Michele Piccardi ,  Xiaojiang Guo ,  Qiang Tang

IPC: H02M3/07

Abstract: An electronic device includes a reconfigurable charge pump including pump units that can be arranged differently for varying an output voltage generated by the reconfigurable charge pump; a pump regulator coupled to the reconfigurable charge pump, the pump regulator configured to monitor the output voltage and turn the reconfigurable charge pump on or off based on the output voltage; and an arrangement control mechanism coupled to the pump regulator, the arrangement control mechanism configured to control operation of the pump regulator based on the output voltage to generate arrangement control output, wherein the arrangement control output controls electrical connections between the pump units.

公开(公告)号：US20190295614A1

公开(公告)日：2019-09-26

申请号：US16429209

申请日：2019-06-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam ,  Qiang Tang ,  Eric N. Lee

IPC: G11C7/22 ,  G11C7/06 ,  G11C8/06 ,  G11C8/18 ,  G11C8/04 ,  G11C7/10

Abstract: A wave pipeline includes a first stage, a plurality of second stages, and a third stage. The first stage receives a data signal representative of data and a clock signal, and may process the data at a first data rate equal to a clock rate of the clock signal. Each second stage may process respective data in response to a respective clock cycle received from the first stage at a second data rate equal to the first data rate times the number of second stages. The third stage may process data received from each second stage at the first data rate. The first stage divides the data signal and the clock signal between the plurality of second stages. The third stage merges the respective data and the respective clock cycles from each of the plurality of second stages to provide a merged data signal and a return clock signal.

公开(公告)号：US20190267094A1

公开(公告)日：2019-08-29

申请号：US16412661

申请日：2019-05-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Xiaojiang Guo ,  Guanglei An ,  Qiang Tang

IPC: G11C16/12 ,  G11C16/14 ,  G11C16/34 ,  G11C16/10 ,  G11C16/08 ,  G11C16/04

Abstract: Methods of operating a memory include determining a target voltage level for an access line voltage, determining a target overdrive voltage level for gating the access line voltage to an access line coupled to a plurality of memory cells, generating a voltage level for the access line voltage in response to its target voltage level and generating a voltage level for gating the access line voltage to the access line in response to the target overdrive voltage level, and applying the access line voltage to the access line while applying the voltage level for gating the access line voltage to a control gate of a string driver connected to the access line.

公开(公告)号：US20190214089A1

公开(公告)日：2019-07-11

申请号：US16178989

申请日：2018-11-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Ramin Ghodsi

IPC: G11C16/10 ,  H03K19/0185 ,  G11C16/26 ,  G11C16/04 ,  H03K19/00

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/26 ,  H03K19/0005 ,  H03K19/018528

Abstract: Methods of operating an integrated circuit device, and integrated circuit devices configured to perform methods, including applying a particular voltage level to a first input of an input/output (I/O) buffer and to a second input of the I/O buffer, determining whether the I/O buffer is deemed to exhibit offset, and applying an adjustment to the I/O buffer offset while applying the particular voltage level to the first input of the I/O buffer and to the second input of the I/O buffer if the I/O buffer is deemed to exhibit offset.

公开(公告)号：US10348527B2

公开(公告)日：2019-07-09

申请号：US15904660

申请日：2018-02-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Xiaojiang Guo ,  Chang Wan Ha

IPC: G11C7/00 ,  H04L25/02 ,  G06F13/40 ,  G11C5/04 ,  G11C29/02 ,  G11C29/50

Abstract: Methods of operating integrated circuit devices include generating a voltage level at a particular node in response to a first voltage level applied to a termination device and a second voltage level applied to a reference resistance; determining whether a plurality of available resistance values of the termination device satisfy a criterion that each available resistance value is either less than a resistance value of the reference resistance, or each available resistance value is greater than the resistance value of the reference resistance; and, when the plurality of available resistance values of the termination device satisfy the criterion, determining whether a voltage level generated at the particular node for a particular available resistance value of the plurality of available resistance values is between a voltage level of a first reference voltage and a voltage level of a second reference voltage.

公开(公告)号：US10270429B1

公开(公告)日：2019-04-23

申请号：US15848796

申请日：2017-12-20

Applicant: Micron Technology, Inc.

Inventor： Guan Wang ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam

IPC: G06F1/10 ,  H03K3/017 ,  H04L25/06 ,  G11C7/22 ,  H03K5/156

Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.

公开(公告)号：US20190074070A1

公开(公告)日：2019-03-07

申请号：US16182355

申请日：2018-11-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Feng Pan ,  Ramin Ghodsi ,  Qiang Tang

IPC: G11C16/34 ,  G11C16/24 ,  G11C16/16 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08

Abstract: Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate drain (SGD) switch and a first select gate source (SGS) switch, a second memory subblock including a second SGD switch and a second SGS switch, and an access line associated with the first and second memory subblocks. The apparatus may include a control unit configured to enable the first and second SGD switches and the first and second SGS switches during a first portion of a read operation and to provide a first voltage on the access line during the first portion. The control unit may be configured to disable the first SGD switch and the first SGS switches during a second portion of the read operation and to provide a second voltage on the access line during the second portion.

公开(公告)号：US10115457B2

公开(公告)日：2018-10-30

申请号：US15444982

申请日：2017-02-28

Applicant: Micron Technology, Inc.

Inventor： Qiang Tang ,  Feng Pan ,  Ramin Ghodsi ,  Mark A. Helm

IPC: G11C11/34 ,  G11C11/56

Abstract: Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to determine a first current on a source line of an array of memory cells, the first current corresponding to a first quantity of memory cells of a group of memory cells that conducts in response to a first sensing voltage applied to an access line and determine a second current on the source line, the second current corresponding to a second quantity of memory cells of the group that conducts in response to a second sensing voltage applied to the access line. The number of apparatuses can include a controller configured to determine at least a portion of a Vt distribution corresponding to the group of memory cells based, at least in part, on the first current and the second current.

公开(公告)号：US20170372784A1

公开(公告)日：2017-12-28

申请号：US15692565

申请日：2017-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Ramin Ghodsi ,  Toru Tanzawa

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C16/26 ,  G11C16/12

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/12 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459

Abstract: Programming methods include applying a voltage to a selected access line commonly connected to a plurality of memory cells, and, while the voltage applied to the selected access line remains at a program voltage without being discharged, electrically connecting a subset of the plurality of memory cells to one data line so that only one memory cell of the subset of the plurality of memory cells is electrically connected to the one data line at a time.

公开(公告)号：US20170285938A1

公开(公告)日：2017-10-05

申请号：US15084979

申请日：2016-03-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric Lee ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Daesik Song

IPC: G06F3/06 ,  G11C16/26 ,  G06F12/08 ,  G11C16/32

CPC classification number: G06F3/061 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0802 ,  G06F2212/222 ,  G06F2212/7203 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  G11C16/26 ,  G11C16/32

Abstract: In an example, a method of operating a memory device to latch data for output from the memory device may include generating a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, generating a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and latching the data in response to the second clock edge of the first clock signal for output from the memory device.