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    Methods Of Forming A Channel Region Of A Transistor And Methods Used In Forming A Memory Array
    22.
    发明申请
    Methods Of Forming A Channel Region Of A Transistor And Methods Used In Forming A Memory Array 审中-公开

    公开(公告)号：US20190198320A1

    公开(公告)日：2019-06-27

    申请号：US15903280

    申请日：2018-02-23

    Applicant: Micron Technology, Inc.

    Inventor： David H. Wells ,  Anish A. Khandekar ,  Kunal Shrotri ,  Jie Li

    IPC: H01L21/02 ,  H01L27/115

    Abstract: A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.

    Integrated structures
    25.
    发明授权
    Integrated structures 有权

    公开(公告)号：US09659949B2

    公开(公告)日：2017-05-23

    申请号：US14666002

    申请日：2015-03-23

    Applicant: Micron Technology, Inc.

    Inventor： Hongbin Zhu ,  Gordon A. Haller ,  Charles H. Dennison ,  Anish A. Khandekar ,  Brett D. Lowe ,  Lining He ,  Brian Cleereman

    IPC: H01L27/115 ,  H01L27/11556 ,  H01L27/11582

    CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

    Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels along sidewalls of the opening. At least one of the cavities is formed to be shallower than one or more others of the cavities. Charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative and conductive levels. Cavities extend into the conductive levels. At least one of the cavities is shallower than one or more others of the cavities by at least about 2 nanometers. Charge-blocking dielectric is within the cavities. Charge-storage structures are within the cavities.

    ON-DIE FORMATION OF SINGLE-CRYSTAL SEMICONDUCTOR STRUCTURES
    27.
    发明公开
    ON-DIE FORMATION OF SINGLE-CRYSTAL SEMICONDUCTOR STRUCTURES 审中-公开

    公开(公告)号：US20230276635A1

    公开(公告)日：2023-08-31

    申请号：US18144708

    申请日：2023-05-08

    Applicant: Micron Technology, Inc.

    Inventor： Jeffery Brandt Hull ,  Anish A. Khandekar ,  Hung-Wei Liu ,  Sameer Chhajed

    IPC: H10B53/20 ,  H01L21/02

    CPC classification number: H10B53/20 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02645

    Abstract: Methods, systems, and devices for on-die formation of single-crystal semiconductor structures are described. In some examples, a layer of semiconductor material may be deposited above one or more decks of memory cells and divided into a set of patches. A respective crystalline arrangement of each patch may be formed based on nearly or partially melting the semiconductor material, such that nucleation sites remain in the semiconductor material, from which respective crystalline arrangements may grow. Channel portions of transistors may be formed at least in part by doping regions of the crystalline arrangements of the semiconductor material. Accordingly, operation of the memory cells may be supported by lower circuitry (e.g., formed at least in part by doped portions of a crystalline semiconductor substrate), and upper circuitry (e.g., formed at least in part by doped portions of a semiconductor deposited over the memory cells and formed with a crystalline arrangement in-situ).

    On-die formation of single-crystal semiconductor structures
    28.
    发明授权
    On-die formation of single-crystal semiconductor structures 有权

    公开(公告)号：US11683937B2

    公开(公告)日：2023-06-20

    申请号：US17397725

    申请日：2021-08-09

    Applicant: Micron Technology, Inc.

    Inventor： Jeffery Brandt Hull ,  Anish A. Khandekar ,  Hung-Wei Liu ,  Sameer Chhajed

    IPC: H10B53/20 ,  H01L21/02

    CPC classification number: H10B53/20 ,  H01L21/0257 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02645

    Abstract: Methods, systems, and devices for on-die formation of single-crystal semiconductor structures are described. In some examples, a layer of semiconductor material may be deposited above one or more decks of memory cells and divided into a set of patches. A respective crystalline arrangement of each patch may be formed based on nearly or partially melting the semiconductor material, such that nucleation sites remain in the semiconductor material, from which respective crystalline arrangements may grow. Channel portions of transistors may be formed at least in part by doping regions of the crystalline arrangements of the semiconductor material. Accordingly, operation of the memory cells may be supported by lower circuitry (e.g., formed at least in part by doped portions of a crystalline semiconductor substrate), and upper circuitry (e.g., formed at least in part by doped portions of a semiconductor deposited over the memory cells and formed with a crystalline arrangement in-situ).

    Vertical transistors
    29.
    发明授权
    Vertical transistors 有权

    公开(公告)号：US11637175B2

    公开(公告)日：2023-04-25

    申请号：US17116120

    申请日：2020-12-09

    Applicant: Micron Technology, Inc.

    Inventor： Yi Fang Lee ,  Hung-Wei Liu ,  Ning Lu ,  Anish A. Khandekar ,  Jeffery B. Hull ,  Silvia Borsari

    IPC: H01L29/04 ,  H01L29/786

    Abstract: A vertical transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The top source/drain region and the channel region have a top interface and the bottom source/drain region and the channel region have a bottom interface. The channel region is crystalline and has an average crystal grain size of its crystal grains that is less than 20 nanometers. The channel region at the top interface or at the bottom interface has greater horizontal texture than volume of the crystal grains in the channel region that is vertically between the crystal grains that are at the top and bottom interfaces. Other embodiments and aspects are disclosed.

    Arrays of elevationally-extending strings of memory cells and methods used in forming an array of elevationally-extending strings of memory cells
    30.
    发明授权
    Arrays of elevationally-extending strings of memory cells and methods used in forming an array of elevationally-extending strings of memory cells 有权

    公开(公告)号：US11600494B2

    公开(公告)日：2023-03-07

    申请号：US17318470

    申请日：2021-05-12

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Gordon A. Haller ,  Tom J. John ,  Anish A. Khandekar ,  Christopher Larsen ,  Kunal Shrotri

    IPC: H01L21/311 ,  H01L27/11556 ,  H01L21/02 ,  H01L27/11582

    Abstract: A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier. Transistor channel material is formed in the individual channel openings elevationally along the etch-stop tier and along the insulative tiers and the wordline tiers that are above and below the etch-stop tier. Arrays independent of method are disclosed.

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