公开(公告)号：US10964475B2

公开(公告)日：2021-03-30

申请号：US16258904

申请日：2019-01-28

Applicant: Micron Technology, Inc.

Inventor： Devesh Dadhich Shreeram ,  Sevim Korkmaz ,  Jian Li ,  Sanjeev Sapra ,  Dewali Ray

IPC: H01L49/02 ,  H01G4/008 ,  H01G4/08

Abstract: Methods, apparatuses, and systems related to forming a capacitor using a sacrificial material are described. An example method includes forming a first silicate material on a substrate. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes forming a sacrificial material on the second nitride material. The method further includes forming a column of capacitor material through the first silicate material, the first nitride material, the second silicate material, the second nitride material, and the sacrificial material. The method further includes removing the sacrificial material to expose a top portion of the capacitor material.

公开(公告)号：US20210043644A1

公开(公告)日：2021-02-11

申请号：US16532019

申请日：2019-08-05

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Merri L. Carlson ,  Anilkumar Chandolu ,  Indra V. Chary ,  David Daycock ,  Harsh Narendrakumar Jain ,  Matthew J. King ,  Jian Li ,  Brett D. Lowe ,  Prakash Rau Mokhna Rau ,  Lifang Xu

IPC: H01L27/11582 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/3213

Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.

公开(公告)号：US10741468B2

公开(公告)日：2020-08-11

申请号：US16229257

申请日：2018-12-21

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li ,  Haojun Zhang ,  Paul A. Silvestri ,  Xiao Li ,  Shijian Luo ,  Luke G. England ,  Brent Keeth ,  Jaspreet S. Gandhi

IPC: H01L23/36 ,  H01L23/367 ,  H01L23/42 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/373

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

公开(公告)号：US10579570B2

公开(公告)日：2020-03-03

申请号：US16215719

申请日：2018-12-11

Applicant: Micron Technology, Inc.

Inventor： Jian Li

IPC: G06F13/40 ,  G06F13/16 ,  G06F11/10 ,  G06F11/07

Abstract: The present disclosure relates generally to semiconductor memory and methods, and more particularly, to apparatuses, and methods for controlling logic die circuitries. One example apparatus comprises a logic die including a first serialization/deserialization (SERDES) component and a second SERDES component coupled to the logic die, and a switch component coupled to the first SERDES component and the second SERDES component configured to activate one of the number of SERDES components.

公开(公告)号：US20190145713A1

公开(公告)日：2019-05-16

申请号：US16247352

申请日：2019-01-14

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li

IPC: F28D15/04 ,  H01L23/427 ,  H01L23/367 ,  F28D15/02

CPC classification number: F28D15/043 ,  F28D15/0233 ,  F28D15/0266 ,  F28D15/046 ,  H01L23/3675 ,  H01L23/427 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die, a second semiconductor die on a base region of the first die, and a thermal transfer device attached to a peripheral region of the first die and extending over the second die. The thermal transfer device includes a conductive structure having an internal cavity and a working fluid at least partially filling the cavity. The conductive structure further includes first and second fluid conversion regions adjacent the cavity. The first fluid conversion region transfers heat from at least the peripheral region of the first die to a volume of the working fluid to vaporize the volume in the cavity, and the second fluid conversion region condenses the volume of the working fluid in the cavity after it has been vaporized.

公开(公告)号：US20180374810A1

公开(公告)日：2018-12-27

申请号：US16102960

申请日：2018-08-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jaspreet S. Gandhi ,  James M. Derderian ,  Sameer S. Vadhavkar ,  Jian Li

IPC: H01L23/00 ,  H01L23/34 ,  H01L23/367 ,  H01L23/48 ,  H01L25/065 ,  H01L25/00 ,  H01L21/78

Abstract: Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.

公开(公告)号：US10162781B2

公开(公告)日：2018-12-25

申请号：US15170183

申请日：2016-06-01

Applicant: Micron Technology, Inc.

Inventor： Jian Li

IPC: G06F13/40 ,  G06F13/16

Abstract: The present disclosure relates generally to semiconductor memory and methods, and more particularly, to apparatuses, and methods for controlling logic die circuitries. One example apparatus comprises a logic die including a first serialization/deserialization (SERDES) component and a second SERDES component coupled to the logic die, and a switch component coupled to the first SERDES component and the second SERDES component configured to activate one of the number of SERDES components.

公开(公告)号：US20180358314A1

公开(公告)日：2018-12-13

申请号：US16104720

申请日：2018-08-17

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  James M. Derderian ,  Sameer S. Vadhavkar ,  Jian Li

IPC: H01L23/00 ,  H01L23/34 ,  H01L23/367 ,  H01L23/48 ,  H01L25/065 ,  H01L25/00 ,  H01L21/78

Abstract: Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.

公开(公告)号：US20170351628A1

公开(公告)日：2017-12-07

申请号：US15170183

申请日：2016-06-01

Applicant: Micron Technology, Inc.

Inventor： Jian Li

IPC: G06F13/40 ,  G06F13/16

CPC classification number: G06F13/4022 ,  G06F13/1605

Abstract: The present disclosure relates generally to semiconductor memory and methods, and more particularly, to apparatuses, and methods for controlling logic die circuitries. One example apparatus comprises a logic die including a first serialization/deserialization (SERDES) component and a second SERDES component coupled to the logic die, and a switch component coupled to the first SERDES component and the second SERDES component configured to activate one of the number of SERDES components.

公开(公告)号：US09837396B2

公开(公告)日：2017-12-05

申请号：US15254586

申请日：2016-09-01

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/00 ,  H01L25/065 ,  H01L25/16 ,  H01L21/56 ,  H01L23/04 ,  H01L21/50 ,  H01L23/36 ,  H01L23/367 ,  H01L21/48

CPC classification number: H01L25/50 ,  H01L21/4882 ,  H01L21/50 ,  H01L21/563 ,  H01L23/04 ,  H01L23/36 ,  H01L23/3675 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/167 ,  H01L2224/16145 ,  H01L2225/06568 ,  H01L2225/06589

Abstract: A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. The assembly further includes a thermal transfer unit having a base attached to the peripheral region of the first die, a cover attached to the base by an adhesive, and a cavity defined by at least cover, wherein the second die is within the cavity. The assembly also includes an underfill in the cavity, wherein a fillet portion of the underfill extends a distance up along a portion of the footing and upward along at least a portion of the base.