公开(公告)号：US20110205719A1

公开(公告)日：2011-08-25

申请号：US13033218

申请日：2011-02-23

申请人： Atsushi Watanabe ,  Seiji Fujiwara

发明人： Atsushi Watanabe ,  Seiji Fujiwara

IPC分类号： H05K7/02

CPC分类号： H01L23/49562 ,  H01L23/3121 ,  H01L23/49513 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2929 ,  H01L2224/29298 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01052 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

摘要： An electronic component is mounted on a circuit board. The electronic component includes: a lead frame including a fixed portion, a lead portion connected to the fixed portion, and a heat-dissipating portion connected to the fixed portion; a semiconductor chip fixed on the fixed portion by a first binder; and an encapsulation resin for encapsulating the fixed portion, the semiconductor chip, and a base portion of the lead portion. A groove is provided in the fixed portion and the heat-dissipating portion of the lead frame. The groove extends from a portion of the fixed portion where the first binder is present toward the heat-dissipating portion.

摘要翻译： 电子部件安装在电路板上。 电子部件包括：引线框架，包括固定部分，连接到固定部分的引线部分和连接到固定部分的散热部分; 通过第一粘合剂固定在固定部分上的半导体芯片; 以及用于封装固定部分，半导体芯片和引线部分的基部的封装树脂。 在引线框架的固定部分和散热部分中设置有凹槽。 凹槽从存在第一粘合剂的固定部分的一部分朝向散热部分延伸。

公开(公告)号：US07973412B2

公开(公告)日：2011-07-05

申请号：US12342347

申请日：2008-12-23

申请人： Seiji Fujiwara ,  Yoshihiro Tomita ,  Akio Furusawa ,  Kenichirou Suetugu

发明人： Seiji Fujiwara ,  Yoshihiro Tomita ,  Akio Furusawa ,  Kenichirou Suetugu

IPC分类号： H01L23/48 ,  H01L21/52 ,  C22C12/00 ,  B23K35/26

CPC分类号： C22C12/00 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29298 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83455 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/01083 ,  H01L2924/3512 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

摘要： In a semiconductor device bonded to a motherboard with a bonding material having a melting point of 200° C. to 230° C., a bonding material 15 which is a die bonding material for bonding a semiconductor element 13 to a semiconductor substrate 11 is a Bi alloy containing 0.8 wt % to 10 wt % of Cu and 0.02 wt % to 0.2 wt % of Ge, so that the bonding material 15 for bonding the semiconductor element 13 to the semiconductor substrate 11 is not melted when the semiconductor device is bonded to the motherboard by reflowing. It is therefore possible to suppress poor connection on the semiconductor element 13, thereby securing the mountability and electrical reliability of the semiconductor device.

摘要翻译： 在用熔点为200℃〜230℃的接合材料接合到母板的半导体器件中，作为用于将半导体元件13接合到半导体基板11的芯片接合材料的接合材料15是 含有0.8重量％〜10重量％的Cu和0.02重量％〜0.2重量％的Ge的Bi合金，使得当将半导体元件13接合到半导体基板11时，用于将半导体元件13接合到半导体基板11的接合材料15不熔化 主板通过回流。 因此，可以抑制半导体元件13的不良连接，从而确保半导体器件的安装性和电可靠性。

公开(公告)号：US20090166876A1

公开(公告)日：2009-07-02

申请号：US12342347

申请日：2008-12-23

申请人： Seiji Fujiwara ,  Yoshihiro Tomita ,  Akio Furusawa ,  Kenichirou Suetugu

发明人： Seiji Fujiwara ,  Yoshihiro Tomita ,  Akio Furusawa ,  Kenichirou Suetugu

IPC分类号： H01L23/48 ,  C22C12/00

CPC分类号： C22C12/00 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29298 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83455 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/01083 ,  H01L2924/3512 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

摘要： In a semiconductor device bonded to a motherboard with a bonding material having a melting point of 200° C. to 230° C., a bonding material 15 which is a die bonding material for bonding a semiconductor element 13 to a semiconductor substrate 11 is a Bi alloy containing 0.8 wt % to 10 wt % of Cu and 0.02 wt % to 0.2 wt % of Ge, so that the bonding material 15 for bonding the semiconductor element 13 to the semiconductor substrate 11 is not melted when the semiconductor device is bonded to the motherboard by reflowing. It is therefore possible to suppress poor connection on the semiconductor element 13, thereby securing the mountability and electrical reliability of the semiconductor device.

摘要翻译： 在用熔点为200℃〜230℃的接合材料接合到母板的半导体器件中，作为用于将半导体元件13接合到半导体基板11的芯片接合材料的接合材料15是 含有0.8重量％〜10重量％的Cu和0.02重量％〜0.2重量％的Ge的Bi合金，使得当将半导体元件13接合到半导体基板11时，用于将半导体元件13接合到半导体基板11的接合材料15不熔化 主板通过回流。 因此，可以抑制半导体元件13的不良连接，从而确保半导体器件的安装性和电可靠性。

公开(公告)号：US20070262409A1

公开(公告)日：2007-11-15

申请号：US11705509

申请日：2007-02-13

申请人： Yoichiro Nozaki ,  Yasuhiro Takehana ,  Akira Oga ,  Toshiyuki Fukuda ,  Seiji Fujiwara

发明人： Yoichiro Nozaki ,  Yasuhiro Takehana ,  Akira Oga ,  Toshiyuki Fukuda ,  Seiji Fujiwara

IPC分类号： H01L23/495

CPC分类号： H01L23/49541 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49568 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/05647 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A lead frame includes: a die pad for holding a semiconductor chip; a radiator plate extending outward from one side face of the die pad and another side face thereof opposite the one side; a plurality of inner leads arranged opposite respective sides of the die pad other than the sides from which the radiator plate extends so as to interpose the die pad; and a plurality of outer leads formed outside the plurality of inner leads and connected to the inner leads. At least one of the plurality of inner leads serves as a ground lead connected to the die pad. In the radiator plate, an island bonding area of which potential is equal to that of the die pad is formed, a first slit is formed around three sides of the island bonding area, and the other side is connected to the radiator plate through a joint part.

摘要翻译： 引线框架包括：用于保持半导体芯片的管芯焊盘; 散热板，其从所述管芯焊盘的一个侧面向外延伸，另一侧面与所述一侧相对; 多个内引线，其布置在所述芯片焊盘的相对侧以外，所述多个内引线除了所述散热板延伸以便插入所述管芯焊盘的侧面之外; 以及多个外引线，其形成在所述多个内引线的外侧并连接到所述内引线。 多个内部引线中的至少一个用作连接到管芯焊盘的接地引线。 在散热板中，形成电位等于芯片焊盘的岛接合面积，在岛接合区域的三侧形成有第一狭缝，另一侧通过接头与散热板连接 部分。

公开(公告)号：US20070126117A1

公开(公告)日：2007-06-07

申请号：US11594098

申请日：2006-11-08

申请人： Seiji Fujiwara

发明人： Seiji Fujiwara

IPC分类号： H01L23/34

CPC分类号： H01L23/49562 ,  H01L23/49531 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/20752 ,  H01L2224/05599

摘要： A center of a substrate having peripheral circuit components mounted thereon is hollowed in a size maintaining a distance for establishing a connection with a semiconductor chip through a conductor such that the semiconductor chip is bonded to a heatsink and the peripheral circuit components are arranged near the semiconductor chip so as to surround the semiconductor chip. Upon adhesion of a conductive paste material, for bonding the substrate to the heatsink having the semiconductor chip mounted thereon in a conductive manner, to a bottom face of the substrate, an adhesive tape is stuck to an edge of the substrate so as to prevent outflow of the conductive paste material, respective terminals are connected through conductors, and both the substrate and the heatsink are sealed with a resin.

摘要翻译： 具有安装在其上的外围电路部件的基板的中心以与半导体芯片连接的距离保持一定距离的尺寸被中空化，使得半导体芯片被接合到散热器，并且外围电路部件布置在半导体附近 芯片，以便围绕半导体芯片。 导电性糊剂材料粘合时，为了将基板与导电性地安装有半导体芯片的散热器粘接在基板的底面，粘合带粘贴到基板的边缘，以防止流出 通过导体连接各个端子，并且用树脂密封基板和散热器。

公开(公告)号：US07081795B2

公开(公告)日：2006-07-25

申请号：US11255998

申请日：2005-10-24

申请人： Toru Matsuura ,  Kaoru Ishida ,  Makoto Sakakura ,  Seiji Fujiwara

发明人： Toru Matsuura ,  Kaoru Ishida ,  Makoto Sakakura ,  Seiji Fujiwara

IPC分类号： H03F1/26

CPC分类号： H03F1/3241 ,  H03F1/3229 ,  H03F1/3247 ,  H03F1/3276 ,  H03F1/3282

摘要： An amplitude frequency characteristic adjustment circuit 106 is provided downstream of and connected to a distortion generation circuit 105. An amplitude difference between low-frequency-side and high-frequency-side distortion voltages is adjusted by the amplitude frequency characteristic adjustment circuit 106, and then their amplitudes and phases are adjusted by a vector adjustment circuit 107. This configuration makes it possible to suppress simultaneously both of low-frequency-side and high-frequency-side distortion voltages of a distortion generated by a wide-band class-AB power amplifier even if they are different in amplitude and phase.

公开(公告)号：US20060061418A1

公开(公告)日：2006-03-23

申请号：US11255998

申请日：2005-10-24

申请人： Toru Matsuura ,  Kaoru Ishida ,  Makoto Sakakura ,  Seiji Fujiwara

发明人： Toru Matsuura ,  Kaoru Ishida ,  Makoto Sakakura ,  Seiji Fujiwara

IPC分类号： H03F1/26

CPC分类号： H03F1/3241 ,  H03F1/3229 ,  H03F1/3247 ,  H03F1/3276 ,  H03F1/3282

摘要： An amplitude frequency characteristic adjustment circuit 106 is provided downstream of and connected to a distortion generation circuit 105. An amplitude difference between low-frequency-side and high-frequency-side distortion voltages is adjusted by the amplitude frequency characteristic adjustment circuit 106, and then their amplitudes and phases are adjusted by a vector adjustment circuit 107. This configuration makes it possible to suppress simultaneously both of low-frequency-side and high-frequency-side distortion voltages of a distortion generated by a wide-band class-AB power amplifier even if they are different in amplitude and phase.

公开(公告)号：US06989713B2

公开(公告)日：2006-01-24

申请号：US11100507

申请日：2005-04-07

申请人： Toru Matsuura ,  Kaoru Ishida ,  Makoto Sakakura ,  Seiji Fujiwara

发明人： Toru Matsuura ,  Kaoru Ishida ,  Makoto Sakakura ,  Seiji Fujiwara

IPC分类号： H03F1/26

CPC分类号： H03F1/3241 ,  H03F1/3229 ,  H03F1/3247 ,  H03F1/3276 ,  H03F1/3282

摘要： An amplitude frequency characteristic adjustment circuit 106 is provided downstream of and connected to a distortion generation circuit 105. An amplitude difference between low-frequency-side and high-frequency-side distortion voltages is adjusted by the amplitude frequency characteristic adjustment circuit 106, and then their amplitudes and phases are adjusted by a vector adjustment circuit 107. This configuration makes it possible to suppress simultaneously both of low-frequency-side and high-frequency-side distortion voltages of a distortion generated by a wide-band class-AB power amplifier even if they are different in amplitude and phase.

摘要翻译： 幅度频率特性调整电路106设置在失真产生电路105的下游并连接到失真产生电路105。 通过幅度频率特性调整电路106调整低频侧和高频侧失真电压之间的幅度差，然后通过矢量调整电路107调整其幅度和相位。 通过这种结构，即使幅度和相位不同，也能同时抑制由宽带AB类功率放大器产生的失真的低频侧和高频侧的失真电压。

公开(公告)号：US06710652B2

公开(公告)日：2004-03-23

申请号：US09961144

申请日：2001-09-21

申请人： Masayuki Miyaji ,  Kaoru Ishida ,  Toshimitsu Matsuyoshi ,  Seiji Fujiwara

发明人： Masayuki Miyaji ,  Kaoru Ishida ,  Toshimitsu Matsuyoshi ,  Seiji Fujiwara

IPC分类号： H03F100

CPC分类号： H03F1/3229 ,  H03F2201/3218

摘要： A feedforward amplifier includes a first power splitter for dividing an input signal into two paths. The first path, in sequence, includes a first vector adjuster, a main amplifier, a second power splitter and a delay circuit. The second path, in sequence, includes a delay circuit, a distortion detecting power combiner, a second vector adjuster and an error amplifier. The distortion detecting power combiner combines a portion of a signal from the first path with a signal in the second path. Each vector adjuster adjusts amplitude and phase of a signal in each path. A distortion suppression power combiner synthesizes a signal in the first path with a signal in the second path. Control is included for stopping operation of the error amplifier or main amplifier based on a predetermined condition.

摘要翻译： 前馈放大器包括用于将输入信号分成两个路径的第一功率分配器。 第一路径依次包括第一矢量调节器，主放大器，第二功率分配器和延迟电路。 第二路径依次包括延迟电路，失真检测功率组合器，第二矢量调节器和误差放大器。 失真检测功率组合器将来自第一路径的信号的一部分与第二路径中的信号组合。 每个矢量调节器调整每个路径中信号的幅度和相位。 失真抑制功率组合器将第一路径中的信号与第二路径中的信号合成。 包括用于基于预定条件停止误差放大器或主放大器的操作的控制。

公开(公告)号：US06507253B1

公开(公告)日：2003-01-14

申请号：US09801141

申请日：2001-03-07

申请人： Toshimitsu Matsuyoshi ,  Toru Matsuura ,  Kaoru Ishida ,  Seiji Fujiwara

发明人： Toshimitsu Matsuyoshi ,  Toru Matsuura ,  Kaoru Ishida ,  Seiji Fujiwara

IPC分类号： H01P118

CPC分类号： H03H7/30

摘要： A delay circuit in which amplitude characteristic and delay time characteristic of the output signals do not have any ripple relative to the length of the transmission line is provided. The delay circuit includes a circuit that makes a part of signals distributed into two parts by the power divider (103) to be identical in amplitude and inverse in phase relative to the component of signals outputted from the terminal-a directly to the terminal-c of the circulator (104). By composing with the power combiner (107) both signals are offset each other at the output terminal. As a result, only the signals that are inputted from the input terminal (101) and transmitted through the circulator (104) and the open-ended transmission line (105) are outputted to the output terminal (102).

摘要翻译： 提供其中输出信号的幅度特性和延迟时间特性相对于传输线的长度没有任何纹波的延迟电路。 该延迟电路包括一个电路，其使由功率分配器（103）分成两部分的信号的一部分相对于从终端a直接输出到终端c的信号的分量在幅度上相位相反， 的循环器（104）。 通过与功率组合器（107）组合，两个信号在输出端子彼此偏移。 结果，只有从输入端（101）输入并通过循环器（104）和开路传输线（105）传输的信号才被输出到输出端（102）。