公开(公告)号：US07196372B1

公开(公告)日：2007-03-27

申请号：US10614177

申请日：2003-07-08

Applicant: Bin Yu ,  Ming-Ren Lin ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic

Inventor： Bin Yu ,  Ming-Ren Lin ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic

IPC: H01L29/788

CPC classification number: H01L29/7887 ,  H01L21/28273 ,  H01L27/11568 ,  H01L29/785

Abstract: A non-volatile memory device includes a substrate, an insulating layer, a fin, an oxide layer, spacers and one or more control gates. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The oxide layer is formed on the fin and acts as a tunnel oxide for the memory device. The spacers are formed adjacent the side surfaces of the fin and the control gates are formed adjacent the spacers. The spacers act as floating gate electrodes for the non-volatile memory device.

Abstract translation: 非易失性存储器件包括衬底，绝缘层，鳍，氧化物层，间隔物和一个或多个控制栅极。 绝缘层形成在基板上，并且鳍形成在绝缘层上。 氧化层形成在翅片上并用作存储器件的隧道氧化物。 间隔件邻近翅片的侧表面形成，并且控制栅极邻近间隔件形成。 间隔件用作非易失性存储器件的浮栅电极。

公开(公告)号：US06800910B2

公开(公告)日：2004-10-05

申请号：US10335474

申请日：2002-12-31

Applicant: Ming-Ren Lin ,  Jung-Suk Goo ,  Haihong Wang ,  Qi Xiang

Inventor： Ming-Ren Lin ,  Jung-Suk Goo ,  Haihong Wang ,  Qi Xiang

IPC: H01L27105

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78603 ,  H01L29/78687

Abstract: A FinFET device employs strained silicon to enhance carrier mobility. In one method, a FinFET body is patterned from a layer of silicon germanium (SiGe) that overlies a dielectric layer. An epitaxial layer of silicon is then formed on the silicon germanium FinFET body. A strain is induced in the epitaxial silicon as a result of the different dimensionalities of intrinsic silicon and of the silicon germanium crystal lattice that serves as the template on which the epitaxial silicon is grown. Strained silicon has an increased carrier mobility compared to relaxed silicon, and as a result the epitaxial strained silicon provides increased carrier mobility in the FinFET. A higher driving current can therefore be realized in a FinFET employing a strained silicon channel layer.

Abstract translation: FinFET器件采用应变硅来增强载流子迁移率。 在一种方法中，FinFET体从覆盖在电介质层上的硅锗层（SiGe）构图。 然后在硅锗FinFET体上形成硅的外延层。 由于本征硅和作为外延硅生长的模板的硅锗晶格的不同维度，在外延硅中引起应变。 与松弛硅相比，应变硅具有增加的载流子迁移率，结果外延应变硅在FinFET中提供增加的载流子迁移率。 因此，可以在采用应变硅沟道层的FinFET中实现更高的驱动电流。

公开(公告)号：US06764898B1

公开(公告)日：2004-07-20

申请号：US10147690

申请日：2002-05-16

Applicant: William G. En ,  Joong S. Jeon ,  Minh Van Ngo ,  Ming-Ren Lin

Inventor： William G. En ,  Joong S. Jeon ,  Minh Van Ngo ,  Ming-Ren Lin

IPC: H01L218242

CPC classification number: H01L21/28273 ,  H01L21/2807 ,  H01L21/28123 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/31122 ,  H01L21/31691 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: The present invention relates to a process of fabricating a semiconductor device, including steps of providing a semiconductor wafer; depositing on the semiconductor wafer at least one layer comprising a high-K dielectric material layer; and subsequently removing a selected portion of the at least one layer comprising a high-K dielectric material by implanting ions into the selected portion, and removing the selected portion by etching. As a result of the implantation, the etch rate of the selected portion is increased relative to an etch rate without the implanting.

Abstract translation: 本发明涉及制造半导体器件的方法，包括提供半导体晶片的步骤; 在半导体晶片上沉积包含高K电介质材料层的至少一层; 并且随后通过将离子注入所选择的部分中去除包含高K电介质材料的至少一层的选定部分，以及通过蚀刻去除所选择的部分。 作为植入的结果，所选择的部分的蚀刻速率相对于没有植入的蚀刻速率而增加。

公开(公告)号：US06291278B1

公开(公告)日：2001-09-18

申请号：US09303694

申请日：1999-05-03

Applicant: Qi Xiang ,  Matthew S. Buynoski ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Matthew S. Buynoski ,  Ming-Ren Lin

IPC: H01L21336

CPC classification number: H01L21/76897 ,  H01L21/28518 ,  H01L21/823871 ,  H01L29/66545

Abstract: A method of fabricating a transistor having shallow source and drain extensions utilizes a self-aligned contact. The drain extensions are provided through an opening between a contact area and the gate structure. A high-K gate dielectric material can be utilized. P-MOS and N-MOS transistors can be created according to the disclosed method.

Abstract translation: 制造具有浅源极和漏极延伸的晶体管的方法利用自对准接触。 漏极延伸部分通过接触区域和栅极结构之间的开口提供。 可以使用高K栅介电材料。 可以根据所公开的方法创建P-MOS和N-MOS晶体管。

公开(公告)号：US06271563B1

公开(公告)日：2001-08-07

申请号：US09122815

申请日：1998-07-27

Applicant: Bin Yu ,  Ming-Ren Lin

Inventor： Bin Yu ,  Ming-Ren Lin

IPC: H01L2976

CPC classification number: H01L29/66643 ,  H01L29/42376 ,  H01L29/4983

Abstract: A MOS transistor having a source and drain extension that are less than 40 nanometers in thickness to minimize the short channel effect. A gate includes a high-K dielectric spacer layer to create depletion regions in the substrate which form the drain and source extensions.

Abstract translation: 具有小于40纳米的源极和漏极延伸的MOS晶体管，以最小化短沟道效应。 栅极包括高K电介质间隔层，以在衬底中产生形成漏极和源极延伸的耗尽区。

公开(公告)号：US06200869B1

公开(公告)日：2001-03-13

申请号：US09187890

申请日：1998-11-06

Applicant: Bin Yu ,  Ming-Ren Lin

Inventor： Bin Yu ,  Ming-Ren Lin

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/2255 ,  H01L29/6656

Abstract: A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a solid-phase impurity source. The solid-phase impurity source can be a doped silicon dioxide layer approximately 300 nm thick. The structure is thermally annealed to drive dopants from the solid-phase impurity source into the source and drain regions. The dopants from the impurity source provide ultra-shallow source and drain extensions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).

Abstract translation: 制造具有超浅源极/漏极结的集成电路的方法利用固相杂质源。 固相杂质源可以是约300nm厚的掺杂二氧化硅层。 该结构被热退火以将来自固相杂质源的掺杂剂驱动到源区和漏区。 来自杂质源的掺杂剂提供超浅源极和漏极延伸。 该过程可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。

公开(公告)号：US06169039A

公开(公告)日：2001-01-02

申请号：US09187169

申请日：1998-11-06

Applicant: Ming-Ren Lin ,  Shekhar Pramanick ,  David Bang

Inventor： Ming-Ren Lin ,  Shekhar Pramanick ,  David Bang

IPC: H01L2131

CPC classification number: H01L21/02118 ,  H01L21/02126 ,  H01L21/02134 ,  H01L21/022 ,  H01L21/02282 ,  H01L21/02351 ,  H01L21/31058 ,  H01L21/312 ,  H01L21/3124 ,  Y02P80/30

Abstract: An integrated circuit and a method of forming an integrated circuit is described. The integrated circuit includes a silicon substrate, a dielectric stack formed on the silicon substrate, and conductive metal lines overlying the silicon substrate. A first layer of low-k dielectric material overlies the at least one conductive metal line, and a second layer of low-k dielectric material overlies the first layer of low-k dielectric material. The first layer of low-k dielectric material is electron beam (E-beam) cured and the second layer of low-k dielectric material is thermally cured.

Abstract translation: 描述集成电路和形成集成电路的方法。 集成电路包括硅衬底，形成在硅衬底上的电介质叠层和覆盖硅衬底的导电金属线。 低k电介质材料的第一层覆盖在至少一个导电金属线上，第二低k电介质材料层覆盖在第一低电介质材料层上。 第一层低k电介质材料是电子束（电子束）固化，第二层低k介电材料被热固化。

公开(公告)号：US6140186A

公开(公告)日：2000-10-31

申请号：US196439

申请日：1998-11-20

Applicant: Ming-Ren Lin ,  Peng Fang ,  Donald L. Wollesen

Inventor： Ming-Ren Lin ,  Peng Fang ,  Donald L. Wollesen

IPC: H01L21/266 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/66659 ,  H01L21/266 ,  H01L21/823814 ,  H01L29/7835

Abstract: Asymmetrically doped source/drain regions of a transistor are formed employing protective insulating layers to prevent a portion of the gate electrode from receiving an excessive impurity implantation dose and penetrating through the underlying gate insulating layer into the semiconductor substrate. Sidewall spacers are employed during heavy implantation.

Abstract translation: 晶体管的不对称掺杂的源极/漏极区域使用保护绝缘层形成，以防止栅电极的一部分接收到过多的杂质注入剂量，并穿过下面的栅极绝缘层进入半导体衬底。 在重植入期间采用侧壁间隔物。

公开(公告)号：US6084271A

公开(公告)日：2000-07-04

申请号：US187892

申请日：1998-11-06

Applicant: Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

Inventor： Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/113 ,  H01L31/119 ,  H01L31/62

CPC classification number: H01L29/6659 ,  H01L29/0649 ,  H01L29/78

Abstract: A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field defect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.

公开(公告)号：US6036875A

公开(公告)日：2000-03-14

申请号：US802738

申请日：1997-02-20

Applicant: Ming-Ren Lin

Inventor： Ming-Ren Lin

IPC: H01L21/033 ,  H01L21/3213 ,  C23F1/00

CPC classification number: H01L21/0338 ,  H01L21/32139

Abstract: A method for ultra-fine patterning of a semiconductor device performs a first, anisotropic etching of a hard mask layer according to a pattern created by lithographic techniques to create lines in the hard mask layer having an initial width. A second, anisotropic etching is performed on the hard mask layer to narrow the lines further than otherwise possible with a single etching according to the patterns created by lithography. Using the narrowed lines created in the hard mask layer, a third, anisotropic etching is performed, this time on the conductor layer shadowed by the narrow lines of the hard mask layer. The third etching creates narrow lines in the conductor layer in accordance with the narrow lines of the hard mask layer.

Abstract translation: 半导体器件的超精细图案化方法根据由光刻技术产生的图案对硬掩模层进行第一次各向异性蚀刻，以在具有初始宽度的硬掩模层中产生线。 第二，在硬掩模层上执行各向异性蚀刻，以根据通过光刻产生的图案，通过单次蚀刻而使线更窄。 使用在硬掩模层中产生的窄线，进行第三次各向异性蚀刻，此时在由硬掩模层的窄线遮蔽的导体层上。 第三蚀刻根据硬掩模层的窄线在导体层中产生窄线。