Method for manufacturing dual damascene wiring in semiconductor device
    22.
    发明授权
    Method for manufacturing dual damascene wiring in semiconductor device 有权
    在半导体器件中制造双镶嵌线的方法

    公开(公告)号:US08916466B2

    公开(公告)日:2014-12-23

    申请号:US13067960

    申请日:2011-07-11

    摘要: A semiconductor device includes a semiconductor substrate, an insulating film formed above the semiconductor substrate, and a multilayered wiring formed in a prescribed area within the insulating film. The multilayered wiring includes a dual damascene wiring positioned on at least one layer of the multilayered wiring. The dual damascene wiring includes an alloy having copper as a principal component. A concentration of at least one metallic element contained as an added component of the alloy in a via connected to the dual damascene wiring is 10% or more higher in a via connected to a wiring whose width exceeds by five or more times a diameter of the via than that in another via connected to another wiring of a smallest width in a same upper wiring layer of the multilayered wiring.

    摘要翻译: 半导体器件包括半导体衬底,形成在半导体衬底上的绝缘膜,以及形成在绝缘膜内的规定区域中的多层布线。 多层布线包括位于多层布线的至少一层上的双镶嵌布线。 双镶嵌线包括以铜为主要成分的合金。 在连接到双镶嵌布线的通孔中作为合金的添加成分含有的至少一种金属元素的浓度在连接到宽度超过五倍或更多倍的布线的通孔中为10%以上 通过连接到多层布线的同一上布线层中的最小宽度的另一布线的通孔。

    Wiring structure and method for manufacturing the same
    23.
    发明授权
    Wiring structure and method for manufacturing the same 有权
    接线结构及其制造方法

    公开(公告)号:US08592303B2

    公开(公告)日:2013-11-26

    申请号:US12715088

    申请日:2010-03-01

    IPC分类号: H01L21/4763

    摘要: There are provided with a wiring structure and a method for manufacturing the same wherein in a wiring structure of multi-layered wiring in which a metal wiring is formed on a substrate forming a semiconductor element thereby obtaining connection of the element, no damage to insulation property between the abutting wirings by occurrence of leakage current and no deterioration of insulation resistance property between the abutting wirings are achieved in case that fine metal wiring is formed in a porous insulation film. The insulation barrier layer 413 is formed between an interlayer insulation film and the metal wiring, in the metal wiring structure on the substrate forming the semiconductor element. The insulation barrier layer enables to reduce leakage current between the abutting wirings and to elevate the insulation credibility.

    摘要翻译: 提供一种布线结构及其制造方法,其中在形成半导体元件的基板上形成金属布线的多层布线的布线结构中,从而获得元件的连接,不会损坏绝缘性能 在多孔绝缘膜中形成细小的金属布线的情况下,可以通过发生漏电流而在邻接布线之间形成邻接布线之间的绝缘电阻特性。 在形成半导体元件的基板上的金属布线结构中,在层间绝缘膜和金属布线之间形成绝缘阻挡层413。 绝缘阻挡层能够减少邻接布线之间的泄漏电流并提高绝缘可靠性。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
    25.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
    半导体器件及其制造方法

    公开(公告)号:US20120097916A1

    公开(公告)日:2012-04-26

    申请号:US13380728

    申请日:2010-06-21

    IPC分类号: H01L47/00 H01L29/08

    摘要: The objective of the present invention is to provide a semiconductor device provided with a resistance-variable element having sufficient switching property and exhibiting high reliability and high densification as well as good insulating property.The present invention provides a semiconductor device comprising a resistance-variable element provided within multiple wiring layers on a semiconductor substrate, wherein the resistance-variable element comprises a laminated structure in which a first electrode, a first ion-conductive layer of valve-metal oxide film, a second ion-conductive layer containing oxygen and a second electrode are laminated in this order, and the wiring of the multiple wiring layers also serves as the first electrode.

    摘要翻译: 本发明的目的是提供一种半导体器件,其具有具有足够的开关性能并且具有高可靠性和高致密度以及良好的绝缘性能的电阻可变元件。 本发明提供一种半导体器件,其包括设置在半导体衬底上的多个布线层内的电阻可变元件,其中所述电阻可变元件包括层压结构,其中第一电极,阀 - 金属氧化物的第一离子传导层 膜,含有氧的第二离子传导层和第二电极按顺序层叠,并且多个配线层的布线也用作第一电极。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
    26.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
    半导体器件及其制造方法

    公开(公告)号:US20100193953A1

    公开(公告)日:2010-08-05

    申请号:US11993285

    申请日:2006-05-23

    IPC分类号: H01L23/532 H01L21/768

    摘要: A trench is formed in an insulation film formed on top of a semiconductor substrate, and a barrier metal film is formed on the surface of the trench. After a copper or copper alloy film is formed on the barrier metal film, an oxygen absorption film in which a standard energy of formation of an oxidation reaction in a range from room temperature to 400° C. is negative, and in which an absolute value of the standard energy of formation is larger than that of the barrier metal film is formed, and the assembly is heated in a temperature range of 200 to 400° C. A semiconductor device can thereby be provided that has highly reliable wiring, in which the adhesion to the barrier metal film in the copper interface is enhanced, copper diffusion in the interface is suppressed, and electromigration and stress migration are prevented.

    摘要翻译: 在形成于半导体衬底顶部的绝缘膜上形成沟槽,并且在沟槽的表面上形成阻挡金属膜。 在阻挡金属膜上形成铜或铜合金膜之后,在室温至400℃的范围内形成氧化反应的标准能量为负的氧吸收膜,其中绝对值 的标准形成能量大于形成阻挡金属膜的能量,并且组件在200至400℃的温度范围内被加热。由此可以提供具有高可靠性布线的半导体器件,其中 增加了铜界面对阻挡金属膜的附着力,抑制了界面的铜扩散,防止了电迁移和应力迁移。

    Wiring structure and method for manufacturing the same
    27.
    发明授权
    Wiring structure and method for manufacturing the same 有权
    接线结构及其制造方法

    公开(公告)号:US07701060B2

    公开(公告)日:2010-04-20

    申请号:US10558367

    申请日:2004-05-28

    IPC分类号: H01L23/48

    摘要: There are provided with a wiring structure and a method for manufacturing the same wherein in a wiring structure of multi-layered wiring in which a metal wiring is formed on a substrate forming a semiconductor element thereby obtaining connection of the element, no damage to insulation property between the abutting wirings by occurrence of leakage current and no deterioration of insulation resistance property between the abutting wirings are achieved in case that fine metal wiring is formed in a porous insulation film. The insulation barrier layer 413 is formed between an interlayer insulation film and the metal wiring, in the metal wiring structure on the substrate forming the semiconductor element. The insulation barrier layer enables to reduce leakage current between the abutting wirings and to elevate the insulation credibility.

    摘要翻译: 提供一种布线结构及其制造方法,其中在形成半导体元件的基板上形成金属布线的多层布线的布线结构中,从而获得元件的连接,不会损坏绝缘性能 在多孔绝缘膜中形成细小的金属布线的情况下,可以通过发生漏电流而在邻接布线之间形成邻接布线之间的绝缘电阻特性。 在形成半导体元件的基板上的金属布线结构中,在层间绝缘膜和金属布线之间形成绝缘阻挡层413。 绝缘阻挡层能够减少邻接布线之间的泄漏电流并提高绝缘可靠性。

    METHOD OF PRODUCING MULTILAYER INTERCONNECTION AND MULTILAYER INTERCONNECTION STRUCTURE
    30.
    发明申请
    METHOD OF PRODUCING MULTILAYER INTERCONNECTION AND MULTILAYER INTERCONNECTION STRUCTURE 审中-公开
    生产多层互连和多层互连结构的方法

    公开(公告)号:US20090014887A1

    公开(公告)日:2009-01-15

    申请号:US12160149

    申请日:2007-01-05

    IPC分类号: H01L21/768 H01L23/522

    摘要: In an insulating film structure having a barrier insulating film, a via interlayer insulating film, a wiring interlayer insulating film, and a hard mask film stacked in this order on an underlayer wiring, a via hole pattern is formed in the insulating film structure, then a groove pattern is formed in the hard mask film, and a grove is formed in the insulating film structure using this as a mask. According to the prior art, the via side wall is oxidized equally severely in the both processes. The trench side wall is oxidized severely in the via first process according to the prior art, whereas, according to the present invention, the oxidation thereof is suppressed to such an extent that an almost non-oxidized state can be created.

    摘要翻译: 在具有阻挡绝缘膜,通孔层间绝缘膜,布线层间绝缘膜和硬掩模膜的绝缘膜结构中,依次层叠在下层布线上,在绝缘膜结构中形成通孔图案,然后, 在硬掩模膜中形成凹槽图案,并且使用其作为掩模在绝缘膜结构中形成凹槽。 根据现有技术,通孔侧壁在两个过程中同样严重氧化。 在根据现有技术的通孔第一工艺中,沟槽侧壁被严重氧化,而根据本发明,其氧化被抑制到几乎可以产生几乎非氧化状态的程度。