公开(公告)号：US10964665B2

公开(公告)日：2021-03-30

申请号：US15408930

申请日：2017-01-18

Applicant: Nthdegree Technologies Worldwide Inc.

Inventor： William Johnstone Ray ,  Richard Austin Blanchard ,  Mark David Lowenthal ,  Bradley Steven Oraw

IPC: H01L23/00 ,  H05K1/02 ,  H01L25/00 ,  H01L25/075 ,  H05K3/12 ,  H01L25/07 ,  H01L25/18 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065 ,  H01L33/20

Abstract: A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. The devices in each group are connected in parallel so that each group acts as a single device. In one embodiment, about 10 devices are contained in each group so the redundancy makes each group very reliable. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.

公开(公告)号：US09913371B2

公开(公告)日：2018-03-06

申请号：US15405601

申请日：2017-01-13

Applicant: Nthdegree Technologies Worldwide Inc.

Inventor： William Johnstone Ray ,  Richard Austin Blanchard ,  Mark David Lowenthal ,  Bradley Steven Oraw

IPC: H05K1/00 ,  H05K1/02 ,  H01L25/07 ,  H01L25/075 ,  H01L25/18 ,  H01L25/00 ,  H01L33/20 ,  H05K1/18 ,  H05K7/00 ,  H01L21/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

CPC classification number: H05K1/0296 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/95 ,  H01L25/0655 ,  H01L25/072 ,  H01L25/0753 ,  H01L25/18 ,  H01L25/50 ,  H01L33/20 ,  H01L2221/68381 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/25105 ,  H01L2224/25174 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/82104 ,  H01L2224/82143 ,  H01L2224/92244 ,  H01L2224/95085 ,  H01L2224/95101 ,  H01L2224/95102 ,  H01L2224/95115 ,  H01L2224/95143 ,  H01L2224/95146 ,  H01L2924/10253 ,  H01L2924/12 ,  H01L2924/1203 ,  H01L2924/12041 ,  H01L2924/13 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091

Abstract: A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. A patterned hydrophobic layer defines the locations of the printed dots of the devices. The devices in each group are connected in parallel so that each group acts as a single device. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.

公开(公告)号：US09572249B2

公开(公告)日：2017-02-14

申请号：US14204800

申请日：2014-03-11

Applicant: Nthdegree Technologies Worldwide Inc.

Inventor： William Johnstone Ray ,  Richard Austin Blanchard ,  Mark David Lowenthal ,  Bradley Steven Oraw

IPC: H05K7/00 ,  H05K1/02 ,  H01L25/00 ,  H01L25/075 ,  H01L33/20 ,  H05K1/18 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L24/95 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/06 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/072 ,  H01L25/0753 ,  H01L25/18 ,  H01L25/50 ,  H01L33/20 ,  H01L2221/68381 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/25105 ,  H01L2224/25174 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/82104 ,  H01L2224/82143 ,  H01L2224/92244 ,  H01L2224/95085 ,  H01L2224/95101 ,  H01L2224/95102 ,  H01L2224/95115 ,  H01L2224/95143 ,  H01L2224/95146 ,  H01L2924/10253 ,  H01L2924/12 ,  H01L2924/1203 ,  H01L2924/12041 ,  H01L2924/13 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H05K1/029 ,  H05K1/0296 ,  H05K3/12

Abstract: A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. The devices in each group are connected in parallel so that each group acts as a single device. In one embodiment, about 10 devices are contained in each group so the redundancy makes each group very reliable. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.

Abstract translation: 可编程电路包括微阵列晶体管或二极管的印刷组阵列。 这些装置被预先形成并印刷成油墨并固化。 每个组中的设备并联连接，以使每个组充当单个设备。 在一个实施例中，每个组中包含约10个设备，因此冗余使得每个组非常可靠。 每个组具有终止于衬底上的贴片区域中的至少一个电引线。 互连导体图案将贴片区域中的组的至少一些引线互连以产生用于通用电路的定制应用的逻辑电路。 这些组也可以互连成逻辑门，并且栅极引线终止于贴片区域。 然后，互连导体图案将形成复合逻辑电路的栅极互连。

公开(公告)号：US09525097B2

公开(公告)日：2016-12-20

申请号：US14214559

申请日：2014-03-14

Applicant: Nthdegree Technologies Worldwide Inc.

Inventor： Tricia Youngbull ,  Bradley Steven Oraw ,  William Johnstone Ray

IPC: H01L27/142 ,  H01L31/0352 ,  H01L31/18 ,  H01L31/0465 ,  H01L31/0463 ,  H01L31/046

CPC classification number: H01L31/1824 ,  H01L27/1421 ,  H01L31/035281 ,  H01L31/03529 ,  H01L31/0443 ,  H01L31/046 ,  H01L31/0463 ,  H01L31/0465 ,  H01L31/18 ,  H01L31/188 ,  Y02E10/50

Abstract: A PV module is formed having an array of PV cells, where the cells are separated by gaps. Each cell contains an array of small silicon sphere diodes (10-300 microns in diameter) connected in parallel. The diodes and conductor layers may be patterned by printing. A continuous metal substrate supports the diodes and conductor layers in all the cells. A dielectric substrate is laminated to the metal substrate. Trenches are then formed by laser ablation around the cells to sever the metal substrate to form electrically isolated PV cells. A metallization step is then performed to connect the cells in series to increase the voltage output of the PV module. An electrically isolated bypass diode for each cell is also formed by the trenching step. The metallization step connects the bypass diode and its associated cell in a reverse-parallel relationship.

Abstract translation: 形成具有PV电池阵列的PV模块，其中电池被间隙分开。 每个电池都包含并联连接的小硅球二极管阵列（直径10-300微米）。 可以通过印刷将二极管和导体层图案化。 连续的金属基板在所有单元中支撑二极管和导体层。 将电介质基板层压到金属基板上。 然后通过在细胞周围的激光烧蚀形成沟槽以切断金属基底以形成电隔离的PV电池。 然后执行金属化步骤以串联连接电池，以增加PV模块的电压输出。 用于每个电池的电隔离旁路二极管也通过开沟步骤形成。 金属化步骤以反平行关系连接旁路二极管及其相关联的电池。

公开(公告)号：US20160218245A1

公开(公告)日：2016-07-28

申请号：US14973683

申请日：2015-12-17

Applicant: Nthdegree Technologies Worldwide Inc.

Inventor： Bradley Steven Oraw

IPC: H01L33/42 ,  H01L33/54 ,  H01L33/62

CPC classification number: H01L33/42 ,  H01L33/20 ,  H01L33/44

Abstract: In one example of forming a printable vertical LED that can emit light from its top and bottom surfaces, a transparent insulating material, such as silicon nitride, is formed over the bottom semiconductor layers of the LED. The insulating material is then patterned to expose portions of the conductive semiconductor layer or a transparent current spreading layer. The shape and thickness of the patterned insulating material over the bottom surface can be selected to achieve a desired orientation of the printed LED and the desired spreading of current. A thin layer of a transparent conductive material is then deposited over the surfaces of the insulating material and the exposed semiconductor surface, including the sidewalls of the openings. The top bump of the LED may be formed using the existing undoped GaN as the patterned insulating material, or an insulating layer may be deposited and patterned.

Abstract translation: 在形成可从其顶表面和底表面发光的可印刷垂直LED的一个实例中，在LED的底部半导体层上方形成诸如氮化硅的透明绝缘材料。 然后将绝缘材料图案化以暴露导电半导体层或透明电流扩展层的部分。 可以选择底表面上的图案化绝缘材料的形状和厚度以实现印刷的LED的期望取向和所需的电流扩散。 然后将透明导电材料的薄层沉积在绝缘材料和暴露的半导体表面的表面上，包括开口的侧壁。 可以使用现有的未掺杂的GaN作为图案化绝缘材料来形成LED的顶部凸起，或者可以沉积和图案化绝缘层。

公开(公告)号：US09082936B2

公开(公告)日：2015-07-14

申请号：US14162116

申请日：2014-01-23

Applicant: Nthdegree Technologies Worldwide Inc.

Inventor： Jeff Baldridge ,  Mark David Lowenthal ,  Bradley Steven Oraw ,  Thomas Frederick Soules

IPC: H01L33/38 ,  H01L27/15 ,  H01L25/075

CPC classification number: H01L33/38 ,  H01L25/0753 ,  H01L27/153 ,  H01L33/62 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

Abstract: A flexible light sheet includes a thin substrate that allows light to pass through it, a transparent first conductor layer overlying the substrate, an array of vertical light emitting diodes (VLEDs) printed as an ink over the first conductor layer, each of the VLEDs having a bottom electrode electrically contacting the first conductor layer, a dielectric material between the VLEDs overlying the first conductor layer, and a transparent second conductor layer overlying the VLEDs and dielectric layer, each of the VLEDs having a top electrode electrically contacting the transparent second conductor layer. Each individual VLED may emit light bidirectionally. The VLEDs are illuminated by a voltage differential between the first conductor layer and the second conductor layer such that bidirectional light passes through the first conductor layer and the second conductor layer. Phosphor layers may be deposited on both sides to create white light using blue VLEDs.

Abstract translation: 柔性光板包括允许光通过它的薄衬底，覆盖衬底的透明第一导体层，在第一导体层上印刷为油墨的垂直发光二极管阵列（VLED），每个VLED具有 电接触第一导体层的底部电极，覆盖第一导体层的VLED之间的介电材料和覆盖在VLED和电介质层上的透明第二导体层，每个VLED具有与透明第二导体层电接触的顶部电极 。 每个单独的VLED可以双向发光。 VLED被第一导体层和第二导体层之间的电压差照亮，使得双向光通过第一导体层和第二导体层。 可以在两侧沉积荧光体层，以使用蓝色VLED形成白光。

公开(公告)号：US20140230207A1

公开(公告)日：2014-08-21

申请号：US14177632

申请日：2014-02-11

Applicant: NTHDEGREE TECHNOLOGIES WORLDWIDE INC.

Inventor： Bradley Steven Oraw ,  Bemly Sujeewa Randeniya ,  Eric William Kahrs

IPC: H05K3/04

CPC classification number: H05K3/048 ,  H05K3/046 ,  H05K2203/0228 ,  H05K2203/0522 ,  H05K2203/1545 ,  Y10T29/302 ,  Y10T156/1082

Abstract: A flex-circuit or a rigid printed circuit board is formed by depositing an adhesive pattern on a top surface of a substrate. The adhesive pattern corresponds to a copper foil pattern to be formed for interconnecting electronic components. A thin copper foil is then laminated over the substrate to adhere the foil to the adhesive pattern. The foil is then peeled off the substrate such that the foil overlying the adhesive pattern remains, and the foil that is not overlying the adhesive pattern is removed. In one embodiment, the foil is cut or weakened along the edges of the adhesive pattern to minimize tearing of the foil. The foil may be first affixed to a sheet for increased mechanical integrity, prior to the foil being laminated over the substrate, followed by kiss-cutting the foil while on the sheet to avoid tearing of the foil during the lift-off step.

Abstract translation: 柔性电路或刚性印刷电路板通过在基板的顶表面上沉积粘合剂图案而形成。 粘合剂图案对应于要形成的用于互连电子部件的铜箔图案。 然后将薄铜箔层压在基板上以将箔粘附到粘合剂图案上。 然后将箔从基材上剥下，使得覆盖粘合剂图案的箔片保留，并且不覆盖粘合剂图案的箔被去除。 在一个实施例中，箔沿着粘合剂图案的边缘被切割或削弱，以最小化箔的撕裂。 在箔被层压在基材上之前，箔可以首先固定到片材上以增加机械完整性，然后在片材上亲吻切割箔片，以避免在剥离步骤期间撕裂箔片。

公开(公告)号：US20140209945A1

公开(公告)日：2014-07-31

申请号：US14162116

申请日：2014-01-23

Applicant: NTHDEGREE TECHNOLOGIES WORLDWIDE INC.

Inventor： Jeff Baldridge ,  Mark David Lowenthal ,  Bradley Steven Oraw ,  Thomas Frederick Soules

IPC: H01L33/38 ,  H01L27/15

CPC classification number: H01L33/38 ,  H01L25/0753 ,  H01L27/153 ,  H01L33/62 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

Abstract: A flexible light sheet includes a thin substrate that allows light to pass through it, a transparent first conductor layer overlying the substrate, an array of vertical light emitting diodes (VLEDs) printed as an ink over the first conductor layer, each of the VLEDs having a bottom electrode electrically contacting the first conductor layer, a dielectric material between the VLEDs overlying the first conductor layer, and a transparent second conductor layer overlying the VLEDs and dielectric layer, each of the VLEDs having a top electrode electrically contacting the transparent second conductor layer. Each individual VLED may emit light bidirectionally. The VLEDs are illuminated by a voltage differential between the first conductor layer and the second conductor layer such that bidirectional light passes through the first conductor layer and the second conductor layer. Phosphor layers may be deposited on both sides to create white light using blue VLEDs.

Abstract translation: 柔性光板包括允许光通过它的薄衬底，覆盖衬底的透明第一导体层，在第一导体层上印刷为油墨的垂直发光二极管阵列（VLED），每个VLED具有 电接触第一导体层的底部电极，覆盖第一导体层的VLED之间的介电材料和覆盖在VLED和电介质层上的透明第二导体层，每个VLED具有与透明第二导体层电接触的顶部电极 。 每个单独的VLED可以双向发光。 VLED被第一导体层和第二导体层之间的电压差照亮，使得双向光通过第一导体层和第二导体层。 可以在两侧沉积荧光体层，以使用蓝色VLED形成白光。

公开(公告)号：US09657903B2

公开(公告)日：2017-05-23

申请号：US14462881

申请日：2014-08-19

Applicant: Nthdegree Technologies Worldwide Inc.

Inventor： Bradley Steven Oraw

IPC: F21K9/00 ,  H01L33/42 ,  H01L25/075 ,  H01L33/44

CPC classification number: F21K9/00 ,  H01L25/0753 ,  H01L33/42 ,  H01L33/44 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a light sheet includes depositing a reflective conductor layer over a substrate, printing a layer of microscopic inorganic LEDs on the conductor layer, depositing a first dielectric layer, having a first index of refraction, over the conductor layer and along sidewalls of the LEDs, and depositing a transparent conductor layer over the LEDs so that the LEDs are connected in parallel. The transparent conductor layer may be a wire mesh with openings. A liquid or paste polymer layer is then deposited over the transparent conductor layer and directly contacts the first dielectric layer. The indices of refraction of both layers are similar to reduce TIR. The top surface of the polymer layer is then molded to contain light extraction features to reduce waveguiding in the light sheet. In another embodiment, the substrate surface is the light exit surface that has the light extraction features.

公开(公告)号：US09443833B2

公开(公告)日：2016-09-13

申请号：US14826688

申请日：2015-08-14

Applicant: Nthdegree Technologies Worldwide Inc.

Inventor： Bradley Steven Oraw

IPC: H01L33/00 ,  H01L25/075 ,  H01L33/62 ,  G09G3/20 ,  H01L23/00 ,  H01L33/42 ,  H01L33/38 ,  H01L33/44 ,  H01L33/40

CPC classification number: H01L25/0753 ,  G09G3/2003 ,  H01L21/568 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0756 ,  H01L33/387 ,  H01L33/405 ,  H01L33/42 ,  H01L33/44 ,  H01L33/62 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/0002 ,  H01L2933/0033 ,  H01L2933/0066 ,  H01L2924/00

Abstract: A first layer of inorganic first vertical LED dies (VLEDs) of a first color is printed on a conductor surface. A first transparent conductor layer is deposited over the first VLEDs to electrically contact top electrodes of the first VLEDs. An electrically insulated second layer of second VLEDs of a second color is printed over the first transparent conductor layer, and an electrically insulated third layer of third VLEDs of a third color is printed over the first transparent conductor layer. For a color display, the VLEDs are printed in an addressable pixel array. Since the VLEDs are printed as an ink, the overlying VLEDs in a pixel are not vertically aligned, so there is little blockage of light. If the structure is used for general illumination, the VLEDs do not need to be printed in pixel areas.

Abstract translation: 在导体表面上印刷第一颜色的第一层无机第一垂直LED管芯（VLED）。 在第一VLED上沉积第一透明导体层以电接触第一VLED的顶部电极。 在第一透明导体层上印刷第二颜色的第二VLED的电绝缘的第二层，并且在第一透明导体层上印刷第三颜色的第三VLED的电绝缘的第三层。 对于彩色显示器，VLED打印在可寻址像素阵列中。 由于VLED被印刷为墨水，像素中的上覆的VLED不垂直对准，所以几乎没有光的阻挡。 如果结构用于一般照明，则VLED不需要在像素区域中打印。