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公开(公告)号：US09508694B2
公开(公告)日：2016-11-29
申请号：US14559609
申请日：2014-12-03
IPC分类号： H01L33/62 , H01L25/075 , H05K1/00 , H01L33/42
CPC分类号： H01L25/0753 , H01L33/42 , H01L33/62 , H01L2924/0002 , H05K1/00 , H01L2924/00
摘要： Relatively small, electrically isolated segments of LED light sheets are fabricated having an anode terminal and a cathode terminal. The segments contain microscopic printed LEDs that are connected in parallel by two conductive layers sandwiching the LEDs. The top conductive layer is transparent. Separately formed from the light sheet segments is a flexible, large area conductor backplane having a single layer or multiple layers of solid metal strips (traces). The segments are laminated over the backplane's metal pattern to supply power to the segment terminals. An adhesive layer secures the segments to the backplane. The metal pattern may connect the segments in series, or parallel, or form an addressable circuit for a display. The segments may be on a common substrate or physically separated from each other prior to the lamination.
摘要翻译： 制造具有阳极端子和阴极端子的相对小的电隔离的LED光片段。 这些段包含通过夹持LED的两个导电层并联连接的微观印刷的LED。 顶层导电层是透明的。 与光片段分开形成的是具有单层或多层固体金属条（迹线）的柔性大面积导体背板。 片段层叠在背板的金属图案上以向片段端子供电。 粘合剂层将片段固定到背板。 金属图案可以将片段串联或并联连接，或形成用于显示器的可寻址电路。 片段可以在共同的衬底上，或在层压之前彼此物理分离。
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公开(公告)号：US09142535B2
公开(公告)日：2015-09-22
申请号：US14150199
申请日：2014-01-08
发明人： Bradley Steven Oraw
IPC分类号： H01L33/00 , H01L25/075 , H01L33/38 , H01L33/42 , H01L33/44
CPC分类号： H01L25/0756 , H01L21/568 , H01L33/387 , H01L33/42 , H01L33/44 , H01L2224/04105 , H01L2224/20 , H01L2224/24137 , H01L2224/73267 , H01L2224/92244 , H01L2924/0002 , H01L2933/0033 , H01L2924/00
摘要： A first layer of first vertical light emitting diodes (VLEDs) is printed on a conductor surface. A first transparent conductor layer is deposited over the first VLEDs to electrically contact top electrodes of the first VLEDs. A second layer of second VLEDs is printed on the first transparent conductor layer. Since the VLEDs are printed as an ink, the second VLEDs are not vertically aligned with the first VLEDs, so light from the first VLEDs is not substantially blocked by the second VLEDs when the VLEDs are turned on. A second transparent conductor layer is deposited over the second VLEDs to electrically contact top electrodes of the second VLEDs. By this structure, the first VLEDs are connected in parallel, the second VLEDs are connected in parallel, and the first layer of first VLEDs and the second layer of second VLEDs are connected in series by the first transparent conductor layer.
摘要翻译： 第一层第一垂直发光二极管（VLED）印在导体表面上。 在第一VLED上沉积第一透明导体层以电接触第一VLED的顶部电极。 在第一透明导体层上印刷第二层第二VLED。 由于VLED被印刷为墨水，所以第二VLED不与第一VLED垂直对准，因此当VLED被打开时，来自第一VLED的光基本上被第二VLED阻挡。 在第二VLED上沉积第二透明导体层以电接触第二VLED的顶部电极。 通过这种结构，第一VLED并联连接，第二VLED并联连接，第一VLED的第一层和第二VLED的第二层通过第一透明导体层串联连接。
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公开(公告)号：US20150069431A1
公开(公告)日：2015-03-12
申请号：US14481393
申请日：2014-09-09
CPC分类号： H01L25/0753 , H01L33/62 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a light sheet includes printing a layer of inorganic LEDs on a first conductive surface of a substrate, depositing a first dielectric layer, and depositing a second conductor layer over the LEDs so that the LEDs are connected in parallel. At least one of the first conductive surface or the second conductor layer is transparent to allow light to escape. A phosphor layer may be formed over the light sheet so that the LED light mixed with the phosphor light creates white light. The flat light sheet is then folded, such as by molding, to form a three-dimensional structure with angled light emitting walls and reflective surfaces to control a directionality of the emitted light and improve the mixing of light. The folds may form rows of angled walls or polygons.
摘要翻译： 形成光片的方法包括在衬底的第一导电表面上印刷无机LED层，沉积第一介电层，以及在LED上沉积第二导体层，使得LED并联连接。 第一导电表面或第二导体层中的至少一个是透明的以允许光逸出。 可以在光片上形成磷光体层，使得与荧光体光混合的LED光产生白光。 然后，例如通过模制将平面光片折叠成具有成角度的发光壁和反射表面的三维结构，以控制发射光的方向性并改善光的混合。 折叠可以形成成行的成角度的墙壁或多边形。
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公开(公告)号：US20140226329A1
公开(公告)日：2014-08-14
申请号：US14162257
申请日：2014-01-23
CPC分类号： F21V23/06 , F21K9/20 , F21K9/64 , F21V21/005 , F21Y2115/10 , H01L25/0753 , H01L2924/0002 , H01L2924/00
摘要： A system of interlocking LED panel tiles includes a first tile having at least one layer of light emitting diodes (LEDs) provided on a substrate, where the substrate is mounted on a substantially rectangular supporting plate having interlocking features. The substrate overlaps the interlocking features. The first tile has a set of positive and negative voltage conductors running between the two sets of opposite edges of the tile as busses. Multiple identical tiles are provided. Each tile has the interlocking features along their edges that firmly physically connect to abutting tiles to create a lamp having any pattern of tiles selected by the user. By interlocking the tiles, the positive and negative conductors are automatically connected to electrically connect the LEDs in the tiles in parallel, and the interlocking features are hidden by the overlying substrate. Additional conductors may be used to provide greater interconnection flexibility.
摘要翻译： 互锁LED面板瓦的系统包括具有设置在基板上的至少一层发光二极管（LED）的第一瓦片，其中基板安装在具有互锁特征的大致矩形的支撑板上。 基板与互锁特征重叠。 第一瓦片具有一组在瓦片的两组相对边缘之间运行的正和负电压导体作为总线。 提供多个相同的瓷砖。 每个瓦片沿其边缘具有互锁特征，其牢固地物理地连接到邻接的瓦片，以产生具有由用户选择的瓦片的任何图案的灯。 通过互锁瓦片，正和负导体自动连接以平行地电连接瓦片中的LED，并且互锁特征被上覆基板隐藏。 可以使用附加导体来提供更大的互连灵活性。
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5.发明申请公开(公告)号：US20180132347A1
公开(公告)日：2018-05-10
申请号：US15868773
申请日：2018-01-11
CPC分类号： H05K1/0296 , H01L21/563 , H01L23/3121 , H01L24/00 , H01L24/06 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/92 , H01L24/95 , H01L25/0655 , H01L25/072 , H01L25/0753 , H01L25/18 , H01L25/50 , H01L33/20 , H01L2221/68381 , H01L2224/06181 , H01L2224/24137 , H01L2224/25105 , H01L2224/25174 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/82101 , H01L2224/82104 , H01L2224/82143 , H01L2224/92244 , H01L2224/95085 , H01L2224/95101 , H01L2224/95102 , H01L2224/95115 , H01L2224/95143 , H01L2224/95146 , H01L2924/10253 , H01L2924/12 , H01L2924/1203 , H01L2924/12041 , H01L2924/13 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091
摘要： A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. A patterned hydrophobic layer defines the locations of the printed dots of the devices. The devices in each group are connected in parallel so that each group acts as a single device. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.
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公开(公告)号：US20170125372A1
公开(公告)日：2017-05-04
申请号：US15408930
申请日：2017-01-18
CPC分类号： H01L24/95 , H01L21/563 , H01L23/3121 , H01L24/06 , H01L24/24 , H01L24/25 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/92 , H01L25/0655 , H01L25/072 , H01L25/0753 , H01L25/18 , H01L25/50 , H01L33/20 , H01L2221/68381 , H01L2224/06181 , H01L2224/24137 , H01L2224/25105 , H01L2224/25174 , H01L2224/32225 , H01L2224/73267 , H01L2224/82101 , H01L2224/82104 , H01L2224/82143 , H01L2224/92244 , H01L2224/95085 , H01L2224/95101 , H01L2224/95102 , H01L2224/95115 , H01L2224/95143 , H01L2224/95146 , H01L2924/10253 , H01L2924/12 , H01L2924/1203 , H01L2924/12041 , H01L2924/13 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H05K1/029 , H05K1/0296 , H05K3/12
摘要： A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. The devices in each group are connected in parallel so that each group acts as a single device. In one embodiment, about 10 devices are contained in each group so the redundancy makes each group very reliable. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.
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7.发明申请PHOTOVOLTAIC MODULE HAVING PRINTED PV CELLS CONNECTED IN SERIES BY PRINTED CONDUCTORS 有权印刷电路连接的印刷光伏电池的光伏组件公开(公告)号：US20170077344A1
公开(公告)日：2017-03-16
申请号：US15359514
申请日：2016-11-22
IPC分类号： H01L31/18 , H01L31/0443 , H01L31/0463 , H01L31/0352
CPC分类号： H01L31/1824 , H01L27/1421 , H01L31/035281 , H01L31/03529 , H01L31/0443 , H01L31/046 , H01L31/0463 , H01L31/0465 , H01L31/18 , H01L31/188 , Y02E10/50
摘要： A PV module is formed having an array of PV cells, where the cells are separated by gaps. Each cell contains an array of small silicon sphere diodes (10-300 microns in diameter) connected in parallel. The diodes and conductor layers may be patterned by printing. A continuous metal substrate supports the diodes and conductor layers in all the cells. A dielectric substrate is laminated to the metal substrate. Trenches are then formed by laser ablation around the cells to sever the metal substrate to form electrically isolated PV cells. A metallization step is then performed to connect the cells in series to increase the voltage output of the PV module. An electrically isolated bypass diode for each cell is also formed by the trenching step. The metallization step connects the bypass diode and its associated cell in a reverse-parallel relationship.
摘要翻译： 形成具有PV电池阵列的PV模块，其中电池被间隙分开。 每个电池都包含并联连接的小硅球二极管阵列（直径10-300微米）。 可以通过印刷将二极管和导体层图案化。 连续的金属基板在所有单元中支撑二极管和导体层。 将电介质基板层压到金属基板上。 然后通过在细胞周围的激光烧蚀形成沟槽，以切断金属基底以形成电隔离的PV电池。 然后执行金属化步骤以串联连接电池，以增加PV模块的电压输出。 用于每个电池的电隔离旁路二极管也通过开沟步骤形成。 金属化步骤以反平行关系连接旁路二极管及其相关联的电池。
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8.发明授权公开(公告)号：US09577007B2
公开(公告)日：2017-02-21
申请号：US14868082
申请日：2015-09-28
CPC分类号： H01L27/153 , H01L27/15 , H01L33/32
摘要： An LED module is disclosed containing an integrated driver transistor (e.g, a MOSFET) in series with an LED. In one embodiment, LED layers are grown over a substrate. The transistor regions are formed over the same substrate. After the LED layers, such as GaN layers, are grown to form the LED portion, a central area of the LED is etched away to expose a semiconductor surface in which the transistor regions are formed. A conductor connects the transistor in series with the LED. Another node of the transistor is electrically coupled to an electrode on the bottom surface of the substrate. In one embodiment, an anode of the LED is connected to one terminal of the module, one current carrying node of the transistor is connected to a second terminal of the module, and the control terminal of the transistor is connected to a third terminal of the module.
摘要翻译： 公开了一种LED模块，其包含与LED串联的集成驱动晶体管（例如，MOSFET）。 在一个实施例中，LED层在衬底上生长。 晶体管区域形成在相同的衬底上。 在诸如GaN层的LED层被生长以形成LED部分之后，将LED的中心区域蚀刻掉以暴露其中形成晶体管区域的半导体表面。 导体将晶体管与LED串联连接。 晶体管的另一个节点电耦合到衬底的底表面上的电极。 在一个实施例中，LED的阳极连接到模块的一个端子，晶体管的一个馈电节点连接到模块的第二端子，并且晶体管的控制端子连接到模块的第三端子 模块。
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公开(公告)号：US20160035924A1
公开(公告)日：2016-02-04
申请号：US14884693
申请日：2015-10-15
CPC分类号： H01L31/0508 , H01L25/0753 , H01L33/42 , H01L33/62 , H01L2924/0002 , H05K1/0283 , H05K1/189 , H05K2201/0108 , H05K2201/10106 , H05K2201/10143 , H05K2203/1545 , H01L2924/00
摘要： Relatively small, electrically isolated LED tiles or PV tiles are fabricated having an anode electrode and a cathode electrode. The LED tiles contain microscopic printed LEDs that are connected in parallel by two conductive layers sandwiching the LEDs. The top conductive layer is transparent. Separately formed from the tiles is a large area backplane having a single layer or multiple layers of metal traces connected to backplane electrodes corresponding to the tile electrodes. Multiple tiles are laminated over the backplane's metal pattern to connect the tile electrodes to the backplane electrodes, such as by a conductive adhesive. The backplane metal pattern may connect the tiles in series and/or parallel, or form an addressable circuit for a display. Groups of tiles may be physically connected to each other prior to the lamination to ease handling and alignment. The backplane has power terminals electrically coupled to the metal traces for receiving power.
摘要翻译： 制造相对较小的电隔离的LED瓦或PV瓦具有阳极电极和阴极电极。 LED瓦片包含由夹持LED的两个导电层并联连接的微观印刷的LED。 顶层导电层是透明的。 与瓦片分开形成的是具有连接到对应于瓦片电极的背板电极的单层或多层金属迹线的大面积背板。 多个瓦片层叠在背板的金属图案上，以将瓦片电极连接到背板电极，例如通过导电粘合剂。 背板金属图案可以将瓦片串联和/或并联连接，或形成用于显示器的可寻址电路。 在层压之前，瓦片组可以彼此物理连接以便于处理和对准。 背板具有电耦合到金属迹线的功率端子用于接收功率。
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公开(公告)号：US20150357315A1
公开(公告)日：2015-12-10
申请号：US14826688
申请日：2015-08-14
发明人： Bradley Steven Oraw
IPC分类号： H01L25/075 , G09G3/20 , H01L33/54 , H01L33/62 , H01L33/48
CPC分类号： H01L25/0753 , G09G3/2003 , H01L21/568 , H01L24/18 , H01L24/19 , H01L24/20 , H01L25/0756 , H01L33/387 , H01L33/405 , H01L33/42 , H01L33/44 , H01L33/62 , H01L2224/04105 , H01L2224/18 , H01L2224/24137 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/92244 , H01L2924/0002 , H01L2933/0033 , H01L2933/0066 , H01L2924/00
摘要： A first layer of inorganic first vertical LED dies (VLEDs) of a first color is printed on a conductor surface. A first transparent conductor layer is deposited over the first VLEDs to electrically contact top electrodes of the first VLEDs. An electrically insulated second layer of second VLEDs of a second color is printed over the first transparent conductor layer, and an electrically insulated third layer of third VLEDs of a third color is printed over the first transparent conductor layer. For a color display, the VLEDs are printed in an addressable pixel array. Since the VLEDs are printed as an ink, the overlying VLEDs in a pixel are not vertically aligned, so there is little blockage of light. If the structure is used for general illumination, the VLEDs do not need to be printed in pixel areas.
摘要翻译： 在导体表面上印刷第一颜色的第一层无机第一垂直LED管芯（VLED）。 在第一VLED上沉积第一透明导体层以电接触第一VLED的顶部电极。 在第一透明导体层上印刷第二颜色的第二VLED的电绝缘的第二层，并且在第一透明导体层上印刷第三颜色的第三VLED的电绝缘的第三层。 对于彩色显示器，VLED打印在可寻址像素阵列中。 由于VLED被印刷为墨水，像素中的上覆的VLED不垂直对准，所以几乎没有光的阻挡。 如果结构用于一般照明，则VLED不需要在像素区域中打印。
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