公开(公告)号：US06590445B2

公开(公告)日：2003-07-08

申请号：US09963412

申请日：2001-09-27

申请人： Naohiro Ueda

发明人： Naohiro Ueda

IPC分类号： G05F302

CPC分类号： G05F3/242

摘要： A reference voltage generation circuit includes a depletion type MOS transistor having a gate connected to a source and functioning as a constant current source. At least two enhancement type MOS transistors are connected to the depletion type MOS transistor, and have different threshold voltages, but substantially the same profiles of channel impurities. A pair of floating gate and control gate may be provided in one of the two enhancement type MOS transistors. One of the thresholds is determined by a difference in a coupling coefficient calculated from an area ratio of the floating gate and control gate to a channel so as to avoid fluctuations in performance of the MOS transistors due to temperature.

公开(公告)号：US08624677B2

公开(公告)日：2014-01-07

申请号：US13416619

申请日：2012-03-09

申请人： Naohiro Ueda

发明人： Naohiro Ueda

IPC分类号： H03F3/14

CPC分类号： H01L23/3121 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/181 ,  H03F3/45183 ,  H03F2203/45674 ,  H03H7/24 ,  H03H2001/0064 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device includes a semiconductor chip in which an internal circuit is formed, with the internal circuit having an output signal that fluctuates due to variation of fluctuation in electrical characteristics of multiple circuit elements constituting the internal circuit; a chip tab on which the semiconductor chip is mounted, with the semiconductor chip completely overlapping the chip tab and the circuit elements in the semiconductor chip arranged on the chip tab, and encapsulation resin within which the semiconductor chip and the chip tab are sealed. A horizontal surface area of the chip tab is smaller than that of the semiconductor chip, and a distance between a periphery of the chip tab and a periphery of the semiconductor chip is sufficient to cause stress exerted on the semiconductor chip by the encapsulation resin to be uniform across the horizontal surface area of the chip tab.

摘要翻译： 半导体器件包括其中形成有内部电路的半导体芯片，内部电路具有由于构成内部电路的多个电路元件的电特性波动的变化而波动的输出信号; 其上安装有半导体芯片的芯片片，其中半导体芯片与芯片片完全重叠，布置在芯片片上的半导体芯片中的电路元件以及半导体芯片和芯片片被密封在其中的密封树脂。 片状突片的水平表面积小于半导体芯片的水平表面积，并且芯片片的周边与半导体芯片的周边之间的距离足以使由封装树脂施加在半导体芯片上的应力为 穿过芯片片的水平表面积均匀。

公开(公告)号：US20120061828A1

公开(公告)日：2012-03-15

申请号：US13228583

申请日：2011-09-09

申请人： Junichi KONISHI ,  Naohiro Ueda

发明人： Junichi KONISHI ,  Naohiro Ueda

IPC分类号： H01L23/48 ,  H01L21/66 ,  H01L21/28

CPC分类号： H01L27/0207 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05026 ,  H01L2224/05073 ,  H01L2224/051 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/061 ,  H01L2224/0612 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device that is resin-sealed in a wafer level after a rewiring layer forming process and a metal post forming process forming a metal post are performed on a semiconductor substrate of the semiconductor device includes devices formed on the semiconductor substrate. Further all of the devices are disposed in respective positions other than positions overlapping a peripheral border of the metal post when viewed from a top of the semiconductor substrate.

摘要翻译： 在半导体器件的半导体衬底上，在重新布线层形成工艺和形成金属柱的金属柱形成工艺之后，在晶片级树脂密封的半导体器件包括在半导体衬底上形成的器件。 此外，当从半导体衬底的顶部观察时，所有器件都设置在与金属柱的外围边界重叠的位置以外的各个位置。

公开(公告)号：US07928445B2

公开(公告)日：2011-04-19

申请号：US12300347

申请日：2008-03-11

申请人： Naohiro Ueda

发明人： Naohiro Ueda

IPC分类号： H01L29/786

CPC分类号： H01L29/7835 ,  H01L21/823456 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/7831 ,  H01L29/7833 ,  H01L29/788

摘要： A disclosed semiconductor device includes a MOS transistor that causes no problems concerning the formation of a thick gate insulating film and that is applicable to high withstand voltage devices. A drain region has a double diffusion structure including an N-drain region 3d and an N+ drain region 11d. A gate electrode includes a first gate electrode 9 formed on an insulating film 7 and a second gate electrode 13 formed on the first gate electrode 9 via a gate electrode insulating film 11. Between the gate insulating film 7 and the N+ source region 11s, a field insulating film 15 is disposed, over which an edge of the first gate electrode 9 is disposed. A gate voltage applied to the second gate electrode 13 via a gate wiring 13g is divided between the gate insulating film 7 and the gate electrode insulating film 11.

摘要翻译： 所公开的半导体器件包括MOS晶体管，其不会形成厚栅极绝缘膜并且适用于高耐压器件。 漏极区域具有包括N沟道区域3d和N +漏极区域11d的双扩散结构。 栅电极包括形成在绝缘膜7上的第一栅电极9和通过栅电极绝缘膜11形成在第一栅电极9上的第二栅极13.在栅绝缘膜7与N +源极区11s之间， 设置场绝缘膜15，在其上设置第一栅电极9的边缘。 通过栅极布线13g施加到第二栅电极13的栅极电压被划分在栅极绝缘膜7和栅电极绝缘膜11之间。

公开(公告)号：US07735375B2

公开(公告)日：2010-06-15

申请号：US12201350

申请日：2008-08-29

申请人： Naohiro Ueda ,  Hirofumi Watanabe

发明人： Naohiro Ueda ,  Hirofumi Watanabe

IPC分类号： G01B7/16

CPC分类号： G01L1/16 ,  G01L1/2293 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

摘要： A disclosed stress-distribution detecting semiconductor package group includes multiple stress-distribution detecting semiconductor packages each formed by resin-encapsulating a stress detecting semiconductor chip of the same size using an identical resin encapsulation structure. Each stress detecting semiconductor chip includes a piezoelectric element for stress detection and at least two electrode pads electrically connected to the piezoelectric element to measure an electrical property of the piezoelectric element. The piezoelectric elements of the stress detecting semiconductor chips are respectively disposed on the corresponding stress detecting semiconductor chips to be located at different positions from one another when superimposed on a single imaginary semiconductor chip plane having the same plane size as that of the stress detecting semiconductor chips.

摘要翻译： 所公开的应力分布检测半导体封装组包括通过使用相同的树脂封装结构树脂密封相同尺寸的应力检测半导体芯片而形成的多个应力分布检测半导体封装。 每个应力检测半导体芯片包括用于应力检测的压电元件和与压电元件电连接以测量压电元件的电性能的至少两个电极焊盘。 应力检测半导体芯片的压电元件分别设置在相应的应力检测半导体芯片上，以在叠加在具有与应力检测半导体芯片相同的平面尺寸的单个虚拟半导体芯片平面上时彼此不同的位置 。

公开(公告)号：US20090309146A1

公开(公告)日：2009-12-17

申请号：US12300347

申请日：2008-03-11

申请人： Naohiro Ueda

发明人： Naohiro Ueda

IPC分类号： H01L27/06 ,  H01L29/78

CPC分类号： H01L29/7835 ,  H01L21/823456 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/7831 ,  H01L29/7833 ,  H01L29/788

摘要： A disclosed semiconductor device includes a MOS transistor that causes no problems concerning the formation of a thick gate insulating film and that is applicable to high withstand voltage devices. A drain region has a double diffusion structure including an N-drain region 3d and an N+ drain region 11d. A gate electrode includes a first gate electrode 9 formed on an insulating film 7 and a second gate electrode 13 formed on the first gate electrode 9 via a gate electrode insulating film 11. Between the gate insulating film 7 and the N+ source region 11s, a field insulating film 15 is disposed, over which an edge of the first gate electrode 9 is disposed. A gate voltage applied to the second gate electrode 13 via a gate wiring 13g is divided between the gate insulating film 7 and the gate electrode insulating film 11.

摘要翻译： 所公开的半导体器件包括MOS晶体管，其不会形成厚栅极绝缘膜并且适用于高耐压器件。 漏极区域具有包括N沟道区域3d和N +漏极区域11d的双扩散结构。 栅电极包括形成在绝缘膜7上的第一栅电极9和通过栅电极绝缘膜11形成在第一栅电极9上的第二栅极13.在栅绝缘膜7与N +源极区11s之间， 设置场绝缘膜15，在其上设置第一栅电极9的边缘。 通过栅极布线13g施加到第二栅电极13的栅极电压被划分在栅极绝缘膜7和栅电极绝缘膜11之间。