摘要:
By providing a safety material, such as an adhesive foil, the probability for transport-related damage or destruction of substrates caused by broken substrates may be significantly reduced.
摘要:
OPC results may be efficiently evaluated on the basis of a test structure containing a plurality of line features with opposing end portions. Thus, for different line parameters, the effect of OPC may be determined for a given critical tip-to-tip distance by determining the leakage behavior of the test assemblies, each having different design parameter values for line width and lateral distance between adjacent lines.
摘要:
By incorporating an etch control material after the formation of a material layer to be patterned, an appropriate material having a highly distinctive radiation wavelength may be used for generating a distinctive endpoint detection signal during an etch process. Advantageously, the material may be incorporated by ion implantation which provides reduced non-uniformity compared to etch non-uniformities, while the implantation process provides the potential for introducing even very “exotic” implantation species. In some embodiments, the substrate-to-substrate uniformity of the patterning of dual damascene structures may be increased.
摘要:
By additionally planarizing the surface topography of a planarization layer, which may be accomplished on the basis of mechanical contact, a uniform force, a polishing process and the like, an enhanced surface topography may be provided which may be advantageously used in subsequent patterning processes, such as photolithography, imprint techniques and the like.
摘要:
By forming metallization structures on the basis of an imprint technique, in which via openings and trenches may be commonly formed, a significant reduction of process complexity may be achieved due to the omission of at least one further alignment process as required in conventional process techniques. Furthermore, the flexibility and efficiency of imprint lithography may be increased by providing appropriately designed imprint molds in order to provide via openings and trenches exhibiting an increased fill capability, thereby also improving the performance of the finally obtained metallization structures with respect to reliability, resistance against electromigration and the like.
摘要:
By providing a plurality of resistors and a plurality of test patterns within a leakage current test structure, the number of probe pads required for estimating the plurality of test patterns may be significantly reduced, wherein, in some illustrative embodiments, several test patterns may be simultaneously assessed on the basis of two probe pads. Consequently, process parameters and/or design parameters for manufacturing metallization structures of semiconductor devices may be efficiently monitored and controlled.
摘要:
Different threshold voltages of transistors of the same conductivity type in a complex integrated circuit may be adjusted on the basis of different Miller capacitances, which may be accomplished by appropriately adapting a spacer width and/or performing a tilted extension implantation. Thus, efficient process strategies may be available to controllably adjust the Miller capacitance, thereby providing enhanced transistor performance of low threshold transistors while not unduly contributing to process complexity compared to conventional approaches in which threshold voltage values may be adjusted on the basis of complex halo and well doping regimes.
摘要:
In a “via first/trench last” approach for forming metal lines and vias in a metallization system of a semiconductor device, a combination of two hard masks may be used, wherein the desired lateral size of the via openings may be defined on the basis of spacer elements, thereby resulting in significantly less demanding lithography conditions compared to conventional approaches.
摘要:
The thickness of drain and source areas may be reduced by a cavity etch used for refilling the cavities with an appropriate semiconductor material, wherein, prior to the epitaxial growth, an implantation process may be performed so as to allow the formation of deep drain and source areas without contributing to unwanted channel doping for a given critical gate height. In other cases, the effective ion blocking length of the gate electrode structure may be enhanced by performing a tilted implantation step for incorporating deep drain and source regions.
摘要:
By providing a protection layer for suppressing stress relaxation in a tensile-stressed dielectric material during a dual stress liner approach, performance of N-channel transistors may be increased, while nevertheless maintaining a high degree of compatibility with conventional dual stress liner approaches.